Four-valued memory circuit using three-peak MOS-NDR devices and circuits

Electronics Letters

Volumn 42, Issue 9, 2006, Pages 514-515

  Gan, K J ^a   Chen, Y H ^a   Tsai, C S ^a   Su, L X ^a  

^a KUN SHAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; MOS DEVICES; STANDARDS;

MEMORY CIRCUIT; NDR DEVICES; THREE-PEAK;

NETWORKS (CIRCUITS);

EID: 33646398921     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20063634     Document Type: Article

References (6)

1. Sen, S., Capasso, F., Cho, A.Y., and Sivco, D.: ' Resonant tunneling device with multiple negative differential resistance: digital and signal processing applications with reduced circuit complexity ', IEEE Trans. Electron Devices, 1987, ED-34, p. 2185-2191
2. Wei, S.J., and Lin, H.C.: ' Multivalued SRAM cell using resonant tunneling diodes ', IEEE J. Solid-State Circuits, 1992, SC-27, p. 212-216
3. Seabaugh, A.C., Kao, Y.C., and Yuan, H.T.: ' Nine-state resonant tunneling diode memory ', IEEE Electron Device Lett., 1992, 13, p. 479-481
4. Choi, S., Lee, B., Kim, T., and Yang, K.: ' CML-type monostable bistable logic element (MOBILE) using InP-based monolithic RTD/HBT technology ', Electron. Lett., 2004, 40, (13), p. 792-793
5. Wu, C.Y., and Lai, K.N.: ' Integrated Λ-type differential negative resistance MOSFET device ', IEEE J. Solid-State Circuits, 1979, 14, p. 1094-1101
6. Gonzalez, A.F., Bhattacharya, M., Kulkarni, S., and Mazumder, P.: ' CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differential-resistance devices ', IEEE J. Solid-State Circuits, 2001, 36, p. 924-932