Digital circuit applications of resonant tunneling devices

Proceedings of the IEEE

Volumn 86, Issue 4, 1998, Pages 664-686

  Mazumder, Pinaki ^a   Kulkarni, Shriram ^a   Bhattacharya, Mayukh ^a   Sun, Jian Ping ^a   Haddad, George I ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Logic circuits; Multivalued logic circuits; Negative resistance circuits; Resonant tunneling devices

Indexed keywords

EID: 0000900676     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.663544     Document Type: Article

References (69)

1. F.-Capasso, S. Sen, F. Beltrani, L. M. Lunardi, A. S. Vengurlekar, P. R. Smith, N. J. Shah, R. J. Malik, and A. Y. Cho, "Quantum functional devices: Resonant-tunneling transistors, circuits with reduced complexity and multiple-valued logic," IEEE Tmns. Electron Devices, vol. 36, pp. 2065-2082, Oct. 1989.
2. L. L. Chang, L. Esaki, and R. Tsu, "Resonant tunneling in semiconductor double barriers," Appl. Pin's. Lett., vol. 24, pp. 593-595, 1974.
3. J. Randall, G. Frazier, A. Seabaugh, and T. Broekaert, "Potential nanoelectronic integrated circuit technologies," Microeleclron. Eng., vol. 32, nos. 1-4, pp. 15-30, Sept. 1996.
4. W. Chcn, G. Munns, X. Wang, and G. Haddad, "Co-integration of high speed InP-based HBT's and RTD's using chemical beam epitaxy," J. Cryst. Growth, vol. 164, nos. 1-4, pp. 454-459, 1996.
5. A. Seabaugh, E. Beam, III, J. Randall, and Y. Kao, "Cointegration of resonant tunneling and double heterojunction bipolar transistors on InP," IEEE Electron Device Lett., vol. 14, pp. 472-174, Oct. 1993.
6. F. Capasso, S. Sen, F. Bcltram, and A. Y. Cho, "Resonant tunneling and supcrlatticc devices: Physics and circuits," in Ph\sics of Quantum Electron Devices, F. Capasso, Ed. Berlin: Springer-Verlag, 1990, ch. 7, pp. 181-252.
7. F. Capasso, K. Mohammed, and A. Y. Cho, "Resonant tunneling through double barriers, perpendicular quantum transport phenomena in superlattices, and their device applications," IEEEJ. Quantum Electron., vol. QE-22, pp. 1853-1869, Sept. 1986.
8. F. Capasso, S. Sen, A. Y. Cho, and D. Sivco, "Resonant tunneling devices with multiple negative differential resistance and demonstration of a three-state memory cell for multiplevalued logic applications," IEEE Electron Device Lett., vol. EDL-8, pp. 297-299, July 1987.
9. S.-J. Wei and H. C. Lin, "Multivalued SRAM cell using resonant tunnelins diodes," IEEE J. Solid-State Circuits, vol. 27, pp. 212-216, Feb. 1992.
10. M.-H. Shieh and H. C. Lin, "A multiple-dimensional multiplestate SRAM cell using resonant tunneling diodes," IEEE J. Solid-State Circuits, vol. 29, pp. 623-630, May 1994.
11. A. C. Seabaugh, Y.-C. Kao, and H.-T. Yuan, "Nine-state resonant tunnelins diode memory," IEEE Electron Device Lett., vol. 13, pp. 479-481, Sept. 1992.
12. W. L. Chen, G. I. Haddad, G. O. Munns, S. Mohan, and P. Mazumder, "InP-based quantum effect devices: Device fabrication and application in digital circuits," in Proc. Int. Electron Devices Materials S\mp., Taipei, Taiwan, Nov. 1992, pp. 359-362.
13. K. Imamura, "Full adder uses RHET's," J. Electron. Eng., vol. 28, no. 299, pp. 76-80, 90, Nov. 1991.
14. N. Yokoyama, S. Muto, H. Ohnishi, K. Imamura, T. Mori, and T. Inata, "Resonant tunneling hot electron transistors (RHET)," in Physics of Quantum Electron Devices, F. Capasso, Ed. Berlin: Springer-Verlag, 1990, ch. 8, pp. 253-270.
15. T. Mori, S. Muto, H. Tamura, and N. Yokoyama, "Static random access memory cell using a double-emitter resonant-tunneling hot electron transistor for gigabit-plus memory applications," Jpn. J. Appl. Ph\s. 1, vol. 33, no. IB, pp. 791-793, Jan. 1994.
16. M. Takatsu, K. Imamura, T. Mori, T. Adachihara, S. Muto, and N. Yokoyama, "Logic circuits using multi-emitter resonanttunneling hot-electron transistors (RHET's)," in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 1994, pp. 124-125.
17. G. I. Haddad, U. K. Reddy, J. P. Sun, and R. K. Mains, "The bound-state resonant tunneling transistor (BSRTT): Fabrication, D.C. I-V characteristics and high-frequency properties," Superlattices Microstructiires, vol. 7, no. 4, pp. 369-374, 1990.
18. W. L. Chen, G. I. Haddad, G. O. Munns, and J. R. East, "Experimental realization of the bound state resonant tunneling transistor," in Proc. 5Isl Ann. Device Research Conf., Santa Barbara, CA, 1993, pp. 2133-2134.
19. S. Mohan, P. Mazumder, and G. I. Haddad, "Ultra-fast pipelined arithmetic using quantum electronic devices," Proc. Inst. Electr. Eng. vol. 141, pt. E, pp. 104-110, Mar. 1994.
20. K. Maezawa and T. Mizutani, "A new resonant tunneling logic gate employing monostable-bistable transition," Jpn. J. Appl. Pli\s., vol. 32, nos. 1A/B, pp. L42-L44, Jan. 1993.
21. K. Chen, T. Akeyoshi, and K. Maezawa, "Monostable-bistable transition logic elements (MOBILE'S) based on monolithic integration of resonant tunneling diodes and FET's," Jpn. J. Appl. Pirn., Part 1, vol. 34, no. 2B, pp. 1199-1203, Feb. 1995.
22. D. Chow", H. Dunlap, W. Williamson, III, S. Enquist, B. Gilbert, S. Subramaniam, P. Lei, and G. Bernstein, "InAs/AlSb/GaSb resonant interband tunneling diodes and Au-on-InAs/AlSbsuperlattice Schottky diodes for logic circuits," IEEE Electron Device Lett., vol. 17, pp. 69-71, Feb. 1996.
23. J. Shcn, S. Tehrani, H. Goronkin, G. Krämer, and R. Tsui, "Exclusive-nor based on resonant intcrband tunneling FET's," IEEE Electron Device Leil.. vol. 17, pp. 94-96, Mar. 1996.
24. K. Chen and M. Yamamoto, "Frequency multipliers using InPbased resonant-tunnclina hish electron mobility transistors," IEEE Electron Device Lett., vol. 17, pp. 235-238, May 1996.
25. J. Yen, Q. Zhang, M. Mondry, P. Chavarkar, E. Hu, S. Long, and U. Mishra, "Monolithic integrated resonant tunneling diode and heterostructure junction field effect transistor circuits," Solid State Electron., vol. 39, no. 10, pp. 1449-1455, Oct.1996.
26. Y. Watanabe, Y. Nakasha, K. Imanishi, and M. Takikawa, "Monolithic integration of resonant tunneling diode and HEMT for low-voltage, low-power digital circuits," IEICE Trans. Electron., vol. E78-C, no. 4, pp. 368-373, Apr. 1995.
27. S. Mohan, P. Mazumder, and G. I. Haddad, "A subnanosecond 32-bit multiplier using negative differential resistance devices," Electro?:. Lett., vol. 27, no. 21, pp. 1929-1931, Oct.1991.
28. J. van der Wagt, H. Tang, T. Broekaert, Y. Kao, and E. Beam, III, "Vertical multi-bit resonant tunneling diode memory cell," in Proc. 54th Ann. Device Research Conf., Santa Barbara, CA, 1996, pp. 168-169.
29. M. Shieh and H. Lin, "Resonant tunneling devices based word memory cell," IEEE Trims. Circuits Svst. I, vol. 43, pp. 583-588, July 1996.
30. L. J. Micheel and M. J. Paulus, "Differential multiple-valued logic usins resonant tunneling diodes," in Proc. 20th Int. S\mp. Multiple-Valued Logic. Charlotte, NC, 1990, pp. 189-195.'
31. T. Hanyu, Y. Yabe, and M. Kameyama, "Multiple-valued programmable logic array based on a resonant tunneling diode model," IEICE Trans. Electron., vol. E76-C, no. 7, pp. 1126-1132, July J993. .
32. H. Tang and H. Lin, "Multi-valued decoder based on resonant tunneling diodes in current tapping mode," in Proc. 26th Int. Svinp. Multiple-Valued Logic, Santiaao de Compostela, 1996, pp. 230-234.
33. T. Waho, K. Chen, and M. Yamamoto, "Novel multiple-valued logic gate using resonant tunneling devices," IEEE Electron Device Lett., vol. 17, pp. 223-225, May 1996.
34. _, "Literal gate using resonant-tunneling devices," in Proc. 26th Int. S\mp. Multiple-Valued Logic, 1996, pp. 68-73.
35. C. E. Chang, P. M. Asbeck, K.-C. Wang, and E. R. Brown, "Analysis of heterojunction bipolar transistor/resonant tunneling diode logic for low-power and high-speed digital applications," IEEE Trans. Electron Devices, vol. 40, pp. 685-691, Apr. 1993.
36. A. C. Seabaugh, A. H. Taddiken, E. A. Beam, III, J. N. Randall, Y. C. Kao, and B. Newell, "Co-integrated resonant tunneling diode and heterojunction bipolar transistor full adder," in Proc. Int. Electron Devices Meeting, Washington, DC, 1993, pp. 419-122.
37. S. Wei, H. Lin, R. Potter, and D. Shupe, "Self-latching A/D converter using resonant tunneling diodes," IEEEJ. Solid-State Circuits, vol. 28, pp. 697-700, June 1993.
38. I. Mehdi, "Device applications of double barrier resonant tunneling structures," Ph.D. dissertation, Univ. Michigan, Ann Arbor, 1990.
39. T. Sollner, "Resonant-tunneling devices and circuits," in Proc. I2th Annual GaAs 1C Svinp.. New Orleans, LA, 1990, pp. 15-18.
40. N. Yokoyama, S. Muto, K. Imamura, M. Takatsu, T. Mori, Y. Sugiyama, Y. Sakuma, H. Nakao, and T. Adachihara, "Quantum functional devices for advanced electronics," in Proc. 7th Int. Conf. Modulated Semiconductor Structures, Madrid, Spain, 1995, pp. 505-511.
41. A. Seabaugh, "Resonant tunneling and quantum integrated circuits," in Proc. IEEE Cornell Conf. Advanced Concepts in High Speed Semiconductor Devices and Circuits, Ithaca, NY, 1995, pp. 455-459.
42. G. Haddad, "Resonant tunneling heterojunction bipolar transistors and their applications in high functionality/speed digital circuits," in P roc. 8th Int. Conf. Indium Phosphide and Related Materials, Schwabisch Mund, Germany, 1996, pp. 129-132.
43. T. Van Duzer, "Superconductor digital IC's," in VLSI Handbook, J. DiGiacomo, Ed. New York: McGraw-Hill, 1989.
44. S. Mohan, P. Mazumder, R. K. Mains, J. P. Sun, and G. I. Haddad, "Logic design based on negative differential resistance characteristics of quantum electronic devices," Proc. Inst. Electr. Eng., vol. 140, pt. G, pp. 383-391, Dec. 1993.
45. W. Williamson, III, "High-speed RTD-based logic for systems applications," in ULTRA Electronics Program Review, ARPA Rep., Oct. 1994.
46. A. Lakhani, H. Hier, and R. Potter, "Three and six logic states by the vertical integration of InAIAs/InGaAs resonant tunneling structures," J. Appl Phys.. vol. 64, pp. 3735-3736, Oct.198S7
47. M. Bhattacharya and P. Mazumder, "Noise margins of threshold logic gates containing resonant tunneling diodes," in Proc. 8ili Great Lakes S\mp. VLSI, Lafayette, LA, 1998.
48. W. Williamson, III, S. Enquist, D. Chow, H. Dunlap, S. Subramaniam, P. Lei, G. Bernstein, and B. Gilbert, "12 GHz clocked operation of ultralow power interband resonant tunneling diode pipelined logic gates," IEEE J. Solid-Stale Circuits, vol. 32, pp. 222-231, Feb. 1997.
49. K. Maezawa, H. Matsuzaki, T. Akeyoshi, J. Osaka, T. Otsuji, and M. Yamamoto, "High-speed and low power D-FF employing MOBILE'S," in Proc. Int. Conf. Solid State Devices anil Materials, Hamamatsu, Japan, 1997.
50. J. P. Hayes, Com/niter Architecture and Organization. New York: McGraw-Hill, 1988.
51. H. Ling, "High-speed binary adder," J. Res. Develop., vol. 25, 'no. 3, pp. 156-166, May 1981.
52. M. Rocchi, High-Speed Digital 1C Technologies. Boston, MA: Artech House, 1990.
53. A. J. Viterbi, CDMA: Principles of Spread Spectrum Communication. Readins, MA: Addison-VVesley, 1995.
54. S. Kulkarni, P. Mazumder, and G. I. Haddad, "A 32-bit ultrafast parallel correlator using resonant tunneling devices," in Proc. Int. Conf, Integrated Micro/iVanotechnolog\ for Space Applications, Houston, TX, 1995, pp. 157-171.
55. S. YVaser and M. J. Flynn, Introduction to Arithmetic for Digital S\stems Designers. New York: Holt, Rinehart and Winston, 1982.
56. P. Y. T. Hsu, J. T. Rahmeh, E. S. Davidson, and J. A. Abraham, 'TIDBITS: Speedup via time-delay bit-slicing in ALU design for VLSI technology," in Proc. 12th Int. Symp. Computer Architecture. Boston, MA, June 1985, pp. 28-35.
57. M. Kameyama, M. Nomura, and T. Higuchi, "Modular design of multiple-valued arithmetic VLSI system using signed-digit number system," in Proc. 20th Int. Svmp. Multiple-Valued Logic, Charlotte, NC, 1990, pp. 355-362."
58. M. Kameyama, T. Hanyu, and T. Higuchi, "Design and implementation of quaternary nMOS integrated circuits for pipelined imace processing," IEEE J. Solid-State Circuits, vol. SC-22, pp. 20-27, Feb. 1987.
59. L. J. Micheel, "Heterojunction bipolar technology for emittercoupled multiple-valued logic in gigahertz adders and multipliers," in Proc. 22nd Int. Symp. Multiple-Valued Logic, Sendai, Japan, 1992, pp. 18-26.
60. T. Baba and T. Uemura, "Multiple-junction surface tunnel transistors for multiple-valued logic circuits," in Proc. 27th Int. S\mp. Multiple-Valued Logic, Antigonish, Canada, 1997, pp. 41-46.
61. L. Micheel, A. Taddiken, and A. Seabaugh, "Multiple-valued logic computation circuits using micro- and nanoelectronic devices," in Proc. 23rd Int. Symp. Afidtiple-Valued Logic, Sacramento, CA, 1993, pp. 164-169.
62. A. Gonzalez and P. Mazumder, "Compact signed-digit adder using multiple-valued logic," in Proc. 17th Conf. Advanced Research in VLSI, Ann Arbor, MI, 1997, pr96-l 13.
63. H. C. Lin, "Resonant tunneling diodes for multi-valued digital applications," in Proc. 24th Int. S\mp. Multiple-Valued Logic, Boston, MA, 1994, pp. 188-195.'
64. H. Chan, S. Mohan, P. Mazumder, and G. I. Haddad, "Compact multiple-valued multiplexers using negative differential resistance devices," IEEE J. Solid-State Circuits, vol. 31, pp. 1151-1156, Aug. 1996.
65. H.-L. E. Chan, S. Mohan, W. L. Chen, P. Mazumder, and G. I. Haddad, "Ultrafast, compact multiple-valued multiplexers using quantum electronic devices," in Proc. Government Microcircuit Applications Conf., San Diego, CA, 1994, pp. 115-118.
66. K. Chen, T. Waho, K. Maczawa, and M. Yamamoto, "Pro.' grammable logic gate based on controlled quenching of seriesconnected negative differential resistance devices," in Proc 54th Ann. Device Research Conf., Santa Barbara, CA, 1996 np ( 170-171.
67. H. Chan, M. Bhattacharya, and P. Mazumder, "Maskprogrammable multiple-valued logic gate using negative differential resistance devices," Proc. hist. Electr. Eng., vol 143, no. 5, pp. 289-294, Oct. 1996.
68. M. Bhattacharya and P. Mazumder, "A multi-valued counter using resonant tunneling diodes," Univ. Michigan, Ann Arbor NDR Group Research Rep., 1994.
69. T.-H. Kuo, H.-C. Lin, R. C. Potter, and D. Schupe, "Multiplevalued counter," IEEE Trans: Computers, vol. 42, pp. 106-109 Jan. 1993.