Barrier lowering and backscattering extraction in short-channel MOSFETs

IEEE Transactions on Electron Devices

Volumn 57, Issue 9, 2010, Pages 2132-2137

  Giusi, Gino ^a   Iannaccone, Giuseppe ^b   Maji, Debabrata ^c   Crupi, Felice ^a  

^a UNIVERSITY OF CALABRIA   (Italy)

^b UNIVERSITY OF PISA   (Italy)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Backscattering; barrier lowering C V measurements; device simulation

Indexed keywords

BACKSCATTERING MODELS; BACKSCATTERING RATIO; BARRIER LOWERING; BIAS POINTS; DEVICE SIMULATIONS; DEVICE-SCALING; EXPERIMENTAL EXTRACTION; EXPERIMENTAL METHODS; EXTRACTION METHOD; GATE LENGTH; INVERSION CHARGE; MOSFETS; NMOSFETS; SUB-BAND APPROXIMATIONS; TRANSPORT MODELS; TRANSPORT PARAMETERS;

MOSFET DEVICES;

BACKSCATTERING;

EID: 77956056185     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2055273     Document Type: Article

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