Study of warm-electron injection in double-gate SONOS by full-band Monte Carlo simulation

IEEE Electron Device Letters

Volumn 29, Issue 11, 2008, Pages 1242-1244

  Giusi, Gino ^a   Iannaccone, Giuseppe ^b   Mohamed, Mohamed ^c   Ravaioli, Umberto ^c  

^a UNIVERSITY OF CALABRIA   (Italy)

^b UNIVERSITY OF PISA   (Italy)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

FinFET memory; Nonvolatile memory; SONOS

Indexed keywords

ATOMS; BOLTZMANN EQUATION; DRAIN CURRENT; ELECTRON INJECTION; ELECTRONS; MOSFET DEVICES;

BIAS CONDITIONS; BOLTZMANN TRANSPORT EQUATIONS; DRAIN BIASES; FINFET MEMORY; GATE CURRENTS; MONTE CARLO SIMULATIONS; NONVOLATILE MEMORY; ORDERS OF MAGNITUDES; PARTICLE DISTRIBUTIONS; PARTICLE ENERGY DISTRIBUTIONS; POSTPROCESSING METHODS; POTENTIAL BARRIERS; SHORT-CHANNEL EFFECTS; SIMULATION RESULTS; SONOS; SONOS MEMORIES; SOURCE VOLTAGES;

MONTE CARLO METHODS;

EID: 84981362639     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2004784     Document Type: Article

References (15)

1. F. Hofmann, M. Specht, U. Dorda, R. Kömmling, L. Dreeskornfeld, J. Kretz, M. Städele, W. Rösner, and L. Risch, "NVM based on FinFET device structures," Solid State Electron., vol. 49, no. 11, pp. 1799-1804, Nov. 2005.
2. S. Lombardo, C. Gerardi, L. Breuil, C. Jahan, L. Perniola, G. Cina, D. Corso, E. Tripiciano, V. Ancarani, G. Iannaccone, G. Iacono, C. Bongiorno, C. Garozzo, P. Barbera, E. Nowak, R. Puglisi, G. A. Costa, C. Coccorese, M. Vecchio, E. Rimini, J. Van Houdt, B. De Salvo, and M. Melanotte, "Advantages of the FinFET architecture in SONOS and nanocrystal memory devices," in IEDM Tech. Dig., Washington, DC, Dec. 2007, pp. 921-924.
3. L. Perniola, E. Nowak, G. Iannaccone, P. Scheiblin, C. Jahan, G. Pananakakis, J. Razafindramora, B. De Salvo, S. Deleonibus, G. Reimbold, and F. Boulanger, "Physical model for NAND operation in SOI and body-tied nanocrystal FinFLASH memories," in IEDM Tech. Dig., Washington, DC, Dec. 2007, pp. 943-946.
4. Z. Han, C. Lin, N. Goldsman, I. Mayergoyz, S. Yu, and M. Stettler, "Gate leakage current simulation by Boltzmann transport equation and its dependence on the gate oxide thickness," in Proc. SISPAD, 1999, pp. 247-250.
5. H. Lin and J. Peng, "An efficient physics-based gate current calculation by solving space-dependent Boltzmann transport equation," in Proc. Univ./Gov./Ind. Microelectron. Symp., 1995, pp. 193-196.
6. C. M. Yih, G. H. Lee, and S. Chung, "A consistent gate and substrate current model for submicron MOSFETs by considering energy transport," in Proc. VLSI Technol., Syst., Appl., 1995, pp. 127-130.
7. A. Harkar, R.W. Kelsall, and J. N. Ellis, "Monte Carlo study of the lateral distribution of gate current density along the channel of submicron LDD MOSFETs," VLSI Des., vol. 13, no. 1-4, pp. 301-304, 2001.
8. Y. Ohkura, C. Suzuki, H. Amakawa, and K. Nishi, "Analysis of gate currents through high-k dielectrics using a Monte Carlo device simulator," in Proc. SISPAD, 2003, pp. 67-70.
9. K. Hasnat, C.-F. Yeap, S. Jallepalli, S. A. Hareland, W.-K. Shih, V. M. Agostinelli, A. F. Tasch, and C. M. Maziar, "Thermionic emission model of electron gate current in submicron NMOSFETs," IEEE Trans. Electron Devices, vol. 44, no. 1, pp. 129-138, Jan. 1997.
10. G. A. Kathawala, B. Winstead, and U. Ravaioli, "Monte Carlo simulations of double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2467-2473, Dec. 2003.
11. C. J. Wordelman and U. Ravaioli, "Integration of a particle-particle-particle-mesh algorithm with the ensemble Monte Carlo method for the simulation of ultra-small semiconductor devices," IEEE Trans. Electron Devices, vol. 47, no. 2, pp. 410-416, Feb. 2000.
12. M. V. Fischetti, S. E. Laux, and E. Crabbé, "Understanding hot-electron transport in silicon devices: Is there a shortcut?" J. Appl. Phys., vol. 78, no. 2, pp. 1058-1087, Jul. 1995.
13. 2/Si structures," Solid State Electron., vol. 38, no. 8, pp. 1465-1471, 1995.
14. P. Palestri et al., "Comparison of modeling approaches for the capacitance-voltage and current-voltage characteristics of advanced gate stacks," IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 106-114, Jan. 2007.
15. L. Breuil et al., "Nitride based FinFLASH memory device using multilevel hot carrier program/erase," in Proc. Non Volatile Semiconductor Memory Workshop, 2007, pp. 46-47.