Built-in self-repair schemes for flash memories

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 8, 2010, Pages 1243-1256

  Hsiao, Yu Ying ^a   Chen, Chao Hsun ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Built in redundancy analysis (BIRA); built in self repair (BISR); flash memory; memory repair; redundancy architecture; yield

Indexed keywords

BUILT-IN REDUNDANCY ANALYSIS; BUILT-IN SELF-REPAIR; BUILT-IN SELF-REPAIR (BISR); COST-EFFECTIVE SOLUTIONS; CRITICAL ISSUES; DEEP SUBMICROMETER; EMBEDDED MEMORIES; MANUFACTURING UNCERTAINTY; MEMORY PRODUCTS; MEMORY REPAIR; MODE OPERATION; NAND FLASH MEMORY; NON-VOLATILE MEMORIES; NOR FLASH MEMORY; ON CHIPS; REDUNDANCY ANALYSIS; SIMULATION RESULT; SIMULATION TOOL; STRONG DEMAND; SYSTEM ON CHIPS; SYSTEM-IN-PACKAGE APPLICATIONS; YIELD LOSS;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; MICROPROCESSOR CHIPS; NAND CIRCUITS; QUALITY ASSURANCE; REDUNDANCY; REPAIR;

FLASH MEMORY;

EID: 77954874311     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2049051     Document Type: Article

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