Raisin: Redundancy analysis algorithm simulation

IEEE Design and Test of Computers

Volumn 24, Issue 4, 2007, Pages 386-396

  Huang, Rei Fu ^a   Li, Jin Fu ^b   Yeh, Jen Chieh ^c   Wu, Cheng Wen ^d  

^a MEDIATEK INC   (Taiwan)

^b NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^c INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^d NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Algorithm simulation; BIRA; BISR; Raisin; Redundancy analysis; Repair rate; Yield

Indexed keywords

ALGORITHM SIMULATION; BIRA; BISR; RAISIN; REDUNDANCY ANALYSIS; REPAIR RATE; YIELD;

ALGORITHMS; DATA STORAGE EQUIPMENT; FLASH MEMORY; INTEGRATED CIRCUITS; REDUNDANCY; REPAIR;

QUALITY ASSURANCE;

EID: 65349110934     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2007.144     Document Type: Article

References (12)

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