A built-in self-repair scheme for NOR-type flash memory

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 114-119

  Hsiao, Yu Ying ^a   Chen, Chao Hsun ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; COST EFFECTIVENESS; INTEGRATED CIRCUIT LAYOUT; REDUNDANCY;

BUILT-IN REDUNDANCY ANALYSIS (BIRA); BUILT-IN SELF-REPAIR (BISR); DEFECTIVE MEMORIES; SOC AND SIP APPLICATIONS;

FLASH MEMORY;

EID: 33751072414     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.5     Document Type: Conference Paper

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