A built-in self-repair design for RAMs with 2-D redundancy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 6, 2005, Pages 742-745

  Li, Jin Fu ^a   Yeh, Jen Chieh ^b   Huang, Rei Fu ^b   Wu, Cheng Wen ^b  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Built in redundancy analysis (BIRA); Built in self repair (BISR); Built in self test (BIST); Embedded memories

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; ONLINE SYSTEMS; REAL TIME SYSTEMS; STATIC RANDOM ACCESS STORAGE; VLSI CIRCUITS;

BUILT-IN REDUNDANCY ANALYSIS (BIRA); BUILT-IN SELF-REPAIR (BISR); BUILT-IN SELF-TEST (BIST); EMBEDDED MEMORIES;

SEMICONDUCTOR STORAGE;

EID: 23744456840     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.848824     Document Type: Article

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