Post-pass binary adaptation for software-based speculative precomputation

Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

Volumn , Issue , 2002, Pages 117-128

  Liao, Steve Shih Wei ^a   Wang, Perry H ^a   Wang, Hong ^a   Hoflehner, Gerolf ^a   Lavery, Daniel ^a   Shen, John P ^a  

^a NONE

Author keywords

Chaining speculative precomputation; Delay minimization; Dependence reduction; Long range thread based prefetching; Loop rotation; Pointer; Post pass; Prediction; Scheduling; Slack; Slicing; Speculation; Triggering

Indexed keywords

ADAPTIVE SYSTEMS; BANDWIDTH; COMPUTER HARDWARE; DATA ACQUISITION; PROGRAM COMPILERS; PROGRAMMING THEORY; SURFACE MOUNT TECHNOLOGY;

SOFTWARE-BASED SPECULATIVE PRECOMPUTATIONS (SSP);

COMPUTER AIDED SOFTWARE ENGINEERING;

EID: 0036036248     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/543552.512544     Document Type: Conference Paper

References (34)

1. The predictability of computations that produce unpredictable outcomes
2. Dynamic program slicing
3. Data prefetching by dependence graph precomputation
4. The intel IA-64 compiler code generator
5. Dynamic speculative precomputation
6. Speculative precomputation: Long-range prefetching of delinquent loads
7. An experimental evaluation of list scheduling
8. Simultaneous multithreading: Multiplying alpha's performance
9. On the importance of points-to analysis and other memory disambiguation methods for C programs
10. A new approach to the maximum-flow problem
11. Hybrid slicing: An approach for refining static slicing using dynamic information
12. SPEC CPU2000: Measuring CPU performance in the new millennium
13. Intel's multi-threading technology
14. Introducing the IA-64 architecture
15. An advanced optimizer for the IA-64 architecture
16. A safe approximate algorithm for interprocedural pointer aliasing
17. SUIF explorer
18. SUIF explorer: An interactive and interprocedural parallelizer
19. Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
20. Hyper-threading technology architecture and microarchitecture
21. Slice processors: An implementation of operation-based prediction
22. Speculative data-driven multithreading
23. Itanium processor microarchitecture
24. Simulation and modeling of a simultaneous multithreaded processor
25. Simultaneous multithreading: Maximizing on-chip parallelism
26. SoftSDV: A presilicon software development environment for the IA-64 architecture
27. Speculative precomputation: Exploring use of multithreading technology for latency
28. Memory latency-tolerance approaches for itanium processors: Out-of-order execution vs. speculative precomputation
29. Program slicing
30. Understanding the backward slices of performance degrading instructions
31. Execution-based prediction using speculative slices