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Volumn 48, Issue 6, 2010, Pages 557-564

Formation of Sn through-silicon-via and its interconnection process for chip stack packages

Author keywords

Electronic materials; Joining; Microelectronic packaging; Scanning electron microscopy; Strength

Indexed keywords


EID: 77954286120     PISSN: 17388228     EISSN: None     Source Type: Journal    
DOI: 10.3365/KJMM.2010.48.06.557     Document Type: Article
Times cited : (17)

References (26)
  • 9
    • 35348851753 scopus 로고    scopus 로고
    • 3D packaging promises performance, reliability gains with small footprints and lower profiles
    • February
    • M. Karnezos, F. Carson, and R. Pendse, "3D Packaging Promises Performance, Reliability Gains with Small Footprints and Lower Profiles", Chip Scale Review, (February 2005).
    • (2005) Chip Scale Review
    • Karnezos, M.1    Carson, F.2    Pendse, R.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.