Electrical characteristics of the three-dimensional interconnection structure for the chip stack package with Cu through vias

Journal of Electronic Materials

Volumn 36, Issue 2, 2007, Pages 123-128

  Lee, Kwang Yong ^a   Oh, Teck Su ^a   Lee, Jae Ho ^a   Oh, Tae Sung ^a  

^a Hong Ik University   (South Korea)

Author keywords

Chip stack package; Cu via; Electroplating; Interconnection; System in package

Indexed keywords

BUMP JOINTS; FLIP CHIP BONDING; HOLE FORMATION; SYSTEM IN PACKAGE;

COPPER; ELECTRIC PROPERTIES; FLIP CHIP DEVICES; HOLE MOBILITY; INTERCONNECTION NETWORKS; REACTIVE ION ETCHING;

CHIP SCALE PACKAGES;

EID: 33947594905     PISSN: 03615235     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11664-006-0020-5     Document Type: Article

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