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Volumn 17, Issue 12, 2007, Pages 855-857
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Suppression of power/ground inductive Impedance and simultaneous switching noise using silicon through-via in a 3-D stacked chip package
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Author keywords
3 D stacked chip package; Power distribution network (PDN) impedance; Silicon through via (STV); Simultaneous switching noise (SSN)
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Indexed keywords
CHIP SCALE PACKAGES;
ELECTRIC POWER DISTRIBUTION;
SILICON;
3-D STACKED CHIP PACKAGE;
POWER DISTRIBUTION NETWORK (PDN) IMPEDANCE;
SILICON THROUGH-VIA (STV) INTERCONNECTION;
SIMULTANEOUS SWITCHING NOISE (SSN);
ELECTRIC IMPEDANCE;
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EID: 36749052413
PISSN: 15311309
EISSN: None
Source Type: Journal
DOI: 10.1109/LMWC.2007.910485 Document Type: Article |
Times cited : (12)
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References (4)
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