Per-thread cycle accounting in SMT processors

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2009, Pages 133-144

  Eyerman, Stijn ^a   Eeckhout, Lieven ^a  

^a GHENT UNIVERSITY   (Belgium)

Author keywords

Cycle accounting; Simultaneous multithreading (SMT); Thread progress aware fetch policy

Indexed keywords

APPLICATION PROGRAMS; HARDWARE; MULTITASKING; PROGRAM PROCESSORS;

ACCOUNTING ARCHITECTURES; AVERAGE PREDICTION ERROR; EXECUTION TIME; FETCH POLICY; SIMULTANEOUS MULTI-THREADING; SIMULTANEOUS MULTITHREADING PROCESSORS; SINGLE-THREADED; SYSTEM SOFTWARES;

COMPUTER ARCHITECTURE;

EID: 67650091396     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508244.1508260     Document Type: Conference Paper

References (29)

1. C. Boneti, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, C.-Y. Cher, and M. Valero. Software-controlled priority characterization of POWER5 processor. In ISCA, pages 415- 426, June 2008.
2. F. J. Cazorla, P. M. W. Knijnenburg, R. Sakellariou, E. Ferńandez, A. Ramirez, and M. Valero. Predictable performance in SMT processors: Synergy between the OS and SMTs. IEEE Transactions on Computers, 55(7):785-799, July 2006. (Pubitemid 43834513)
3. F. J. Cazorla, A. Ramirez, M. Valero, and E. Fernandez. Dynamically controlled resource allocation in SMT processors. In MICRO, pages 171-182, Dec. 2004. (Pubitemid 40927696)
4. F. J. Cazorla, A. Ramirez, M. Valero, P.M. W. Knijnenburg, R. Sakellariou, and E. Ferńandez. QoS for high-performance SMT processors in embedded systems. IEEE Micro, 24(4):24-31, July 2004.
5. S. Choi and D. Yeung. Learning-based SMT processor resource distribution via hill-climbing. In ISCA, pages 239-250, June 2006. (Pubitemid 46016619)
6. Y. Chou, B. Fahs, and S. Abraham. Microarchitecture optimizations for exploiting memory-level parallelism. In ISCA, pages 76-87, June 2004.
7. E. Cota-Robles. Priority Based Simultaneous Multi-Threading, Dec. 2003. United States Patent No. 6,658,447 B2.
8. J. Dean, J. E. Hicks, C. A. Waldspurger, W. E. Weihl, and G. Chrysos. ProfileMe: Hardware support for instruction-level profiling on out-of-order processors. In MICRO, Dec. 1997.
9. J. Emer. EV8: The post-ultimate alpha. Keynote presentation at PACT, Sept. 2001.
10. S. Eyerman and L. Eeckhout. A memory-level parallelism aware fetch policy for SMT processors. In HPCA, pages 240- 249, Feb. 2007. (Pubitemid 47208168)
11. S. Eyerman and L. Eeckhout. System-level performance metrics for multi-program workloads. IEEE Micro, 28(3):42-53, May/June 2008.
12. S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith. A performance counter architecture for computing accurate CPI components. In ASPLOS, pages 175-184, Oct. 2006. (Pubitemid 47168399)
13. A. Fedorova, M. Seltzer, and M. D. Smith. A non-workconserving operating system scheduler for SMT processors. In WIOSCA, in conjunction with ISCA, June 2006.
14. B. A. Fields, R. Bodik, M. D. Hill, and C. J. Newburn. Interaction cost and shotgun profiling. ACM Transactions on Architecture and Code Optimization, 1(3):272-304, Sept. 2004.
15. R. Gabor, S. Weiss, and A. Mendelson. Fairness enforcement in switch on event multithreading. ACM Transactions on Architecture and Code Optimization (TACO), 4(3):34, Sept. 2007.
16. R. Jain, C. J. Hughes, and S. V. Adve. Soft real-time scheduling on simultaneous multithreaded processors. In Proceedings of the 23rd IEEE International Real-Time Systems Symposium, pages 134-145, Dec. 2002.
17. T. S. Karkhanis and J. E. Smith. A first-order superscalar processor model. In ISCA, pages 338-349, June 2004.
18. K. Luo, J. Gummaraju, and M. Franklin. Balancing throughput and fairness in SMT processors. In ISPASS, pages 164-171, Nov. 2001.
19. A. Mericas. Performance monitoring on the POWER5 microprocessor. In L. K. John and L. Eeckhout, editors, Performance Evaluation and Benchmarking, pages 247-266. CRC Press, 2006.
20. M. K. Qureshi, D. N. Lynch, O. Mutlu, and Y. N. Patt. A case for MLP-aware cache replacement. In ISCA, pages 167-177, June 2006. (Pubitemid 46016613)
21. S. E. Raasch and S. K. Reinhardt. The impact of resource partitioning on SMT processors. In PACT, pages 15-26, Sept. 2003.
22. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In ASPLOS, pages 45-57, Oct. 2002. (Pubitemid 44892222)
23. A. Snavely and D. M. Tullsen. Symbiotic jobscheduling for simultaneous multithreading processor. In ASPLOS, pages 234-244, Nov. 2000. (Pubitemid 32470901)
24. A. Snavely, D. M. Tullsen, and G. Voelker. Symbiotic jobscheduling with priorities for a simultaneous multithreading processor. In SIGMETRICS, pages 66-76, June 2002. (Pubitemid 35009510)
25. W. Stallings. Operating Systems: Internals and Design Principles. Prentice Hall, fifth edition, 2005.
26. D. Tullsen. Simulation and modeling of a simultaneous multithreading processor. In Proceedings of the 22nd Annual Computer Measurement Group Conference, Dec. 1996.
27. D. M. Tullsen and J. A. Brown. Handling long-latency loads in a simultaneous multithreading processor. In MICRO, pages 318-327, Dec. 2001. (Pubitemid 34086877)
28. D.M. Tullsen, S. J. Eggers, J. S. Emer, H.M. Levy, J. L. Lo, and R. L. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In ISCA, pages 191-202, May 1996.
29. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In ISCA, pages 392-403, June 1995.