Rate-based QoS techniques for cache/memory in CMP platforms

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2009, Pages 479-488

  Herdrich, Andrew ^a   Illikkal, Ramesh ^a   Iyer, Ravi ^a   Newell, Don ^a   Chadha, Vineet ^a   Moses, Jaideep ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Cache; Clock gating; DVFS; Frequency scaling; Memory; P states; Performance differentiation; QoS; Rate control; T states

Indexed keywords

CLOCK GATING; CLOCK MODULATION; CPU CORES; FREQUENCY-SCALING; GLOBAL/LOCAL; MULTI-PROCESSORS; PERFORMANCE MANAGEMENT; POWER MANAGEMENT TECHNIQUES; POWER MANAGEMENTS; PRIORITY TASKS; PROCESSING RATES; RATE CONTROLS; RESOURCE CONTENTION; RESOURCE MONITORING; RUNNING-IN; THROTTLING MECHANISM;

CLOCKS; DENSE WAVELENGTH DIVISION MULTIPLEXING; ELECTRIC POWER MEASUREMENT; ENERGY MANAGEMENT; INTELLIGENT CONTROL; MICROPROCESSOR CHIPS; NANOTECHNOLOGY;

CACHE MEMORY;

EID: 70449711364     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1542275.1542342     Document Type: Conference Paper

References (34)

1. ACPI Specification at http://www.acpi/info/spec.htm
2. P. Apparao, et al, "Characterization and Analysis of a Server Consolidation Benchmark" to appear in 2008 International Conference on Virtual Execution Environments (VEE 2008)
3. W. Bircher, and L. John, "Analysis of dynamic power management on multi-core processors," In Proceedings of the 22nd Annual international Conference on Supercomputing (ICS '08), 2008.
4. J. Chang, and G. Sohi, "Cooperative cache partitioning for chip multiprocessors," In Proceedings of the 21st Annual international Conference on Supercomputing (ICS), 2007.
5. D. Chandra, et al, "Predicting inter-thread cache contention on a chip multiprocessor architecture", 11th Int'l Symp. on High Performance Computer Architecture (HPCA), Feb, 2005
6. F. Guo, Y Solihin, L Zhao, R Iyer. "A Framework for Providing Quality of Service in Chip Multi-Processors". IEEE Micro 2007.
7. Intel Corporation. "Intel Dual-Core Processors," http://www.intel.com/technology/computing/dual-core/
8. C. Isci, et al., "Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management," MICRO-39, Dec 2006
9. C. Isci, et al, "An Analysis of Multi-Core Global Power Management Policies," MICRO-39, Dec 2006
10. R. Iyer, "CQoS: A Framework for Enabling QoS in Shared Caches of CMP Platforms," 18th Annual Int'l Conference on Supercomputing (ICS'04), July 2004.
11. R. Iyer, et al, "Datacenter-on-chip Architectures : Tera-scale Challenges and Opportunities" Intel Technology Journal, 2007
12. R. Iyer et al, "QoS Policies and Architecture for Cache/Memory in CMP Platforms," ACM SIGMETRICS 2007
13. H. Kannan, F. Guo, L. Zhao, R. Illikkal, R. Iyer, et al., "From Chaos to QoS: Case Studies in CMP Resource Management," 2nd Workshop on Design, Architecture and Simulation of CMP Platforms (dasCMP/Micro), Dec 2006
14. S. Kim, D. Chandra, and Y. Solihin, "Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture", 13th International Conference on Parallel Architectures and Complication Technique (PACT), Sep-Oct 2004
15. P. Kongetira, K. Aingaran, K. Olukotun, "Niagara: A 32-Way Multithreaded Processor," IEEE Micro. 2005
16. K. Lee, T. Lin and C. Jen. An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC. IEEE Trans. On Circuits and Systems for Video Technology, May 2005
17. Charles Lefurgy, Xiaorui Wang, and Malcolm Ware, "Serverlevel Power Control ", 4th IEEE Conference on Autonomic Computing (ICAC'07), 2007
18. S. Manne, A. Klauser, and D. Grunwald, "Pipeline Gating: Speculation Control for Energy Reduction," 25th International Symposium on Computer Architecture, June 1998.
19. J. Matthews, et al., "Quantifying the Performance Isolation Properties of Virtualization Systems, VMware and Solaris Containers," Workshop on Experimental Computer Science, 2007
20. th International Symposium on Microarchitecture (MICRO), December 2007.
21. G. Neiger et al, "Intel Virtualization Technology: Hardware Support for Efficient Processor Virtualization," Intel Technology Journal, August 2006.
22. K. J. Nesbit, et al, "Fair Queuing Memory Systems", MICRO 2006
23. K. J. Nesbit et al, "Virtual Private Caches", ISCA 2007
24. Pointers to all SPEC CPU2000 material and results http://www.spec.org/ cpu/
25. Patsy K. Popa "X3 Managing Server Energy Consumption Using IBM PowerExecutive" http://www-07.ibm.com/systems/includes/content/x/about/pdf/ XSW02410USEN.pdf
26. Power and Thermal Management in the Intel® Core™ Duo Processor. Intel Technology Journal, 2006
27. M. K. Qureshi and Yale N. Patt, "Utility-Based Cache Partitioning: Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches", MICRO 2006
28. N. Rafique, et al, "Architecture Support for OS-Driven CMP Cache Management", 15th Int'l Conf. on Parallel Architectures and Compilation Techniques, Sept 2006.
29. P. Ranganathan, P. Leech, et al. Ensemble-level power management for dense blade servers. In ISCA, 2006
30. L. Sha, R. Rajkumar and J. P. Lehoczky. Priority Inheritance Protocols: An Approach to Real-Time Synchronization. IEEE Transactions on Computers, Sept 1990.
31. J. Sharkey et al, "Evaluating design tradeoffs in on-chip power management for CMPs" ISLPED 2007
32. H. Tsao, "IBM @eServer p5 570 Server Consolidation Using POWER5", White Paper, IBM Corporation
33. L. Zhao et al, "CacheScouts : Fine-Grain Monitoring of Shared Caches in CMP Platforms", 16th Int'l Conference on Parallel Architectures and Compilation Techniques (PACT), 2007
34. H. Zhang. Service Disciplines for Guaranteed Performance Service in Packet-switching Networks. In Proc. of IEEE, Oct. 1995