Transaction level modeling and design space exploration for SOC test architectures

Proceedings of the Asian Test Symposium

Volumn , Issue , 2009, Pages 200-205

  Chang, Chin Yao ^a   Hsiao, Chih Yuan ^a   Lee, Kuen Jong ^a   Su, Alan P ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

Electronic system level (ESL); SOC testing; Test architecture; Test platform; Transaction level modeling (TLM)

Indexed keywords

ELECTRONIC SYSTEM LEVEL; SOC TESTING; TEST ARCHITECTURE; TEST PLATFORMS; TRANSACTION LEVEL MODELING;

DESIGN; ELECTRONICS ENGINEERING; PROGRAMMABLE LOGIC CONTROLLERS; SPACE RESEARCH; SYSTEM THEORY; SYSTEMS ANALYSIS;

TESTING;

EID: 77951149196     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2009.33     Document Type: Conference Paper

References (19)

1. M. Radetzki and R. S. Khaligh, "Accuracy-Adaptive Simulation of Transaction Level Models," Design, Automation and Test in Europe, pp. 788-791, 2008.
2. A. Kasuya and T. Tesfaye, "Verification Methodologies in a TLM-to-RTL Design Flow," Design Automation Conference, pp. 199-204, 2007.
3. D. Shin, A. Gerstlauer, J. Peng, R. Domer and D. Gajski, "Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration," International Conference Hardware/Software Codesign and System Synthesis, pp. 64-69, 2006.
4. S. Pasricha, N. Dutt, M. Ben-Romdhane, "Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration," Design Automation Conference, pp. 113-118, 2004.
5. N. Dhanwwada, I.-C. Lin, and V. Narayanan, "A Power Estimation Methodology for SystemC Transaction Level Models," International Conference Hardware/Software Codesign and System Synthesis, pp. 142-147, 2005.
6. L. Cai and D. Gajski, "Transaction Level Modeling: An Overview," International Conference on Hardware/Software Codesign and System Synthesis, pp. 19-24, 2003.
7. Y. Zorian, E. J. Marinissen and S. Dey, "Testing embedded-core-based system chips," IEEE Computer, Vol. 32, Issue 6, pp. 52-60, June 1999.
8. Y. Zorian, "Testing the monster chip," IEEE Spectrum, Vol. 36, Issue 7, pp. 54-60, July 1999.
9. IEEE Computer Society, "1500 IEEE Std. Testability Method for Embedded Core-based Integrated Circuits," 2005.
10. IEEE Computer Society, "1149.1 IEEE standard test access port and boundary-scan architecture," 2001.
11. A. Krstic, W.-C. Lai, L. Chen, K.-T. Cheng, and S.Dey, "Embedded Software-based Self-Testing for SoC Design," Design Automation Conference, pp. 355-360, 2002.
12. J.-R. Huang, M. K. Iyer, and K.-T. Cheng, "A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs," VLSI Test Symposium, pp. 198-203, 2001.
13. M. Benabdenbi, A. Greiner, F. Pecheux, E. Viaud, and M. Tuna, "STEPS: Experimenting a New Software-based strategy for Testing SoCs Containing P1500-compliant IP Cores," Design, Automation and Test in Europe, pp. 712-713, 2004.
14. C.-Y. Lo, C.-H. Wang, K.-L. Cheng, J.-R. Huang, C.-W. Wang, S.-M. Wang, and C.-W. Wu, "STEAC: A Platform for Automatic SOC Test Integration," IEEE Trans. on VLSI Systems, pp. 541-545, May 2007.
15. K.-J. Lee, C.-Y. Chu, Y.-T. Hong, "An Embedded Processor Based SOC Test Platform," International Symposium on Circuits and Systems, pp. 2983-2986, 2005.
16. S. K. Goel, E. J. Marinissen, A. Sehgal, and K. Chakrabarty, "Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling," IEEE Trans. on Computers, pp. 409-423, March 2009.
17. S. K. Goel and E. J. Marinissen, "Cluster-Based Test Architecture Design for System-on-Chip," VLSI Test Symposium, pp. 259-264, 2002.
18. ARM Website, http://www.arm.com/
19. T.-Y. Hsieh, K.-J. Lee, and J.-J. You, "Test Efficiency Analysis and Improvement of SOC Test Platforms," Asian Test Symposium, pp. 463-466, 2007.