STEPS: Experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 712-713

  Benabdenbi, M ^a   Greiner, A ^a   Pecheux F ^a   Viaud, E ^a   Tuna, M ^a  

^a UNIVERSITÉ PIERRE ET MARIE CURIE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED MICROPROCESSORS; SERIAL INTERFACE LAYERS (SIL); BUS-BASED; CONTROL COMMAND; CONTROLLER INTERFACES; IP CORE; SOC TESTS; TEST COMPONENTS; TEST DATA;

BENCHMARKING; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; DATA REDUCTION; INTERFACES (COMPUTER); NETWORK PROTOCOLS; RANDOM ACCESS STORAGE; EXHIBITIONS;

MICROPROCESSOR CHIPS; COMPUTER PERIPHERAL EQUIPMENT;

EID: 3042653189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268943     Document Type: Conference Paper

References (3)

1. A. Krstic, L. Chen, W.-C Lai, K.-T Cheng, and S. Dey. Embedded Software-Based Self-Test for Programmable' Core-Based Designs. IEEE Design and Test of Computers, pages 18-26, july-august 2002.
2. Erik Jan Marinissen et al. On IEEE P1500's Standard for Embedded Core Test. Journal of Electronic Testing: Theory and Applications, 18(4/5):365-383, August 2002.
3. Sandeep Kumar Goel and Erik Jan Marinissen. Effective and Efficient Test Architecture Design for SOCs. In Proceedings IEEE International Test Conference (ITC), pages 529-538, Baltimore, MD, October 2002.