STEAC: A platform for automatic SOC test integration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 5, 2007, Pages 541-545

  Lo, Chih Yen ^a   Wang, Chen Hsing ^a   Cheng, Kuo Liang ^a   Huang, Jing Reng ^a   Wang, Chih Wea ^a   Wang, Shin Moe ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Core test language (CTL); IEEE 1500; Logic testing; Scan test; System on chip (SOC); Test access mechanism (TAM)

Indexed keywords

AUTOMATION; COMPUTER AIDED SOFTWARE ENGINEERING; ELECTRONICS ENGINEERING; EMBEDDED SYSTEMS; INPUT OUTPUT PROGRAMS; SOFTWARE TESTING;

CORE TEST LANGUAGE (CTL); LOGIC TESTING; SCAN TESTING; SYSTEM-ON-CHIP (SOC); TEST ACCESS MECHANISM (TAM);

MICROPROCESSOR CHIPS;

EID: 34249792687     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.893662     Document Type: Article

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