Verification methodologies in a TLM-to-RTL design flow

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 199-204

  Kasuya, Atsushi ^a   Tesfaye, Tesh ^a  

^a JEDA Technologies Inc   (United States)

Author keywords

Assertion; PV; PVT; SystemC; TLM; Verification

Indexed keywords

ABSTRACT MODELS; ASSERTION; SYSTEMC; TLM;

ABSTRACTING; CHIP SCALE PACKAGES; COMPUTER AIDED DESIGN; MATHEMATICAL MODELS; SOFTWARE ENGINEERING;

SYSTEM PROGRAM DOCUMENTATION;

EID: 34547277473     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375152     Document Type: Conference Paper

References (13)

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13. TLA Reuse method., JEDA Technologies, Inc. White Paper