Efficient microarchitectural vulnerabilities prediction using boosted regression trees and patient rule inductions

IEEE Transactions on Computers

Volumn 59, Issue 5, 2010, Pages 593-607

  Li, Bin ^a   Duan, Lide ^a   Peng, Lu ^a  

^a LOUISIANA STATE UNIVERSITY   (United States)

Author keywords

Hardware reliability; Modeling and predicti; Modeling of computer architecture

Indexed keywords

ACCURATE PREDICTION; ARCHITECTURAL VULNERABILITY FACTOR; BOOSTED REGRESSION TREES; CLOCK FREQUENCY; COMPUTER ARCHITECTS; EARLY DESIGN STAGES; FEATURE SIZES; HARDWARE RELIABILITY; INDIVIDUAL PERFORMANCE; MODEL SIZE; MODEL STABILITY; MODERN PROCESSORS; NON-PARAMETRIC; PERFORMANCE METRICS; PREDICTIVE MODELING; PROGRAM EXECUTION; QUANTITATIVE COMPARISON; RULE INDUCTION; RULE INDUCTION METHODS; RUNTIMES; TRANSIENT FAULTS; TREE-BASED;

COMPUTER HARDWARE; FAULT TREE ANALYSIS; FORECASTING; QUALITY ASSURANCE; REGRESSION ANALYSIS; RELIABILITY;

COMPUTER ARCHITECTURE;

EID: 77950332817     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2009.140     Document Type: Article

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