Computing accurate AVFs using ACE analysis on performance models: A rebuttal

IEEE Computer Architecture Letters

Volumn 7, Issue 1, 2008, Pages 21-24

  Biswas, Arijit ^a   Racunas, Paul ^a   Emer, Joel ^a   Mukherjee, Shubhendu S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Measurement; Modeling; Performance; Reliability; Simulation

Indexed keywords

ARCHITECTURAL VULNERABILITY FACTORS (AVF); ARCHITECTURALLY CORRECT EXECUTION; HARDWARE STRUCTURES; IPC (INSTRUCTIONS PER CYCLE); LOW LEVEL DETAILS; MICRO ARCHITECTURES; PERFORMANCE MODELLING; TRANSIENT FAULTS; USER VISIBLE ERRORS;

ALUMINUM; ATMOSPHERICS; COMPUTATIONAL METHODS; MICROPROCESSOR CHIPS; MODAL ANALYSIS; MULTITASKING; PIPELINES;

ERROR ANALYSIS;

EID: 44849084462     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2007.19     Document Type: Article

References (6)

1. A. Biswas, P. Racunas, R. Cheveresan, J. Emer, S.S. Mukherjee, R. Rangan, "Computing Architectural Vulnerability Factors for Address-Based Structures", 32nd Annual International Symposium on Computer Architecture (ISCA), 2005
2. S.S. Mukherjee, C.T. Weaver, J. Emer, S.K. Reinhardt, T. Austin, "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-performance Microprocessor," 36th Annual. International Symposium, on Microarchitecture (MICRO), December 2003.
3. P. Racunas, K. Constantinides, S. Manne, S. S. Mukherjee, "Perturbation-based Fault Screening," 13th Annual International High-Performance Computer Architecture (HPCA), Feb. 2007.
4. N. Wang, A. Mahesri, S.J. Patel, "Examining ACE Analysis Reliability Estimates Using Fault-Injection", 34th Annual International Symposium on Computer Architecture (ISCA), 2007
5. N. Wang, M. Fertig, S. Patel, "Y-Branches: When You Come to a Fork in the Road, Take It," 12th International. Conference on Parallel Architectures and Compilation Techniques (PACT), 2003.
6. N. Wang, S.J. Patel, "RESTORE: Symptom based soft error detection in microprocessors", DSN 2005, June 2005