An analysis of microarchitecture vulnerability to soft errors on simultaneous multithreaded architectures

ISPASS 2007: IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2007, Pages 169-178

  Zhang, Wangyuan ^a   Fu, Xin ^a   Li, Tao ^a   Fortes, José ^a  

^a University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROARCHITECTURE; MULTITHREADED ARCHITECTURES; MULTITHREADED EXECUTION; SEMICONDUCTOR TRANSIENT FAULTS; SOFT ERROR VULNERABILITY;

MULTITASKING; PROGRAM PROCESSORS; RELIABILITY ANALYSIS; SEMICONDUCTOR DEVICES; TRANSIENT ANALYSIS;

MICROPROCESSOR CHIPS;

EID: 36949040595     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2007.363747     Document Type: Conference Paper

References (25)

1. P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi, Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic, In Proceedings of the International Conference on Dependable Systems and Networks, 2002.
2. G. A. Reis, J. Chang, N. Vachharajani, R. Rangan, D. I. August and S. S. Mukherjee, Design and Evaluation of Hybrid Fault-Detection Systems, In proceeding of International Symposium on Computer Architecture, 2005.
3. N. J. Wang, J. Quek, T. M. Rafacz and S. J. Patel, Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline, In proceeding of International Conference on Dependable Systems and Networks, 2004.
4. S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin, A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor, In Proceedings of the International Symposium on Microarchitecture, 2003.
5. A. Biswas, R. Cheveresan, J. Emer, S. S. Mukherjee, P. B. Racunas and R. Rangan, Computing Architectural Vulnerability Factors for Address-Based Structures, In Proceedings of the International Symposium on Computer Architecture, 2005.
6. C. Weaver, J. Emer, S. S. Mukherjee, and S. K. Reinhardt, Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor, In Proceedings of the International Symposium on Computer Architecture, 2004.
7. X. D. Li, S. V. Adve, P. Bose, and J. A. Rivers, SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors, In Proceedings of the International Conference on Dependable Systems and Networks, 2005.
8. X. Fu, J. Poe, T. Li and J. Fortes, Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior, In Proceedings of the International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 2006
9. D. Tullsen, S. Eggers, and H. Levy, Simultaneous Multithreading: Maximizing On-Chip Parallelism, In Proceedings of the International Symposium on Computer Architecture, 1995.
10. P. Kongetira, K. Aingaran, and K. Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, vol. 25, no. 2, pp. 21-29, Mar/Apr, 2005.
11. D. Marr, F. Binns, D. Hill, G. Hinton, D. Koufaty, J. Miller, and M. Upton, Hyper-Threading Technology Architecture and Microarchitecture, Intel Technology Journal, 6(1), Feb. 2002.
12. J. Seng, D. Tullsen, and G. Cai, Power-Sensitive Multithreaded Architecture, In Proceedings of the International Conference on Computer Design, 2000.
13. J. Hasan, A. Jalote, T. N. Vijaykumar, and C. Brodley, Heat Stroke: Power-Density-based Denial of Service in SMT, In Proceedings of the International Symposium on High-Performance Computer Architecture, 2005.
14. K. Luo, J. Gummaraju, and M. Franklin, Balancing Throughput and Fairness in SMT Processors, In Proceedings of the International Symposium on Performance Analysis of Systems and Software, 2001.
15. S. Raasch and S. Reinhardt, The Impact of Resource Partitioning on SMT Processors, In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2003.
16. F. Cazorla, E. Fernandez, A. Ramirez, and M. Valero, Dynamically Controlled Resource Allocation in SMT Processors, In Proceedings of the International Symposium on Microarchitecture, 2004.
17. E. W. Czeck and D. Siewiorek, Effects of Transient Gate-level Faults on Program Behavior, In Proceedings of the International Symposium on Fault-Tolerant Computing, 1990.
18. Joseph Sharkey, M-Sim: A Flexible, Multithreaded Architectural Simulation Environment, Technical Report CS-TR-05-DP01, Department of Computer Science, State University of New York at Binghamton, 2005.
19. D. Tullsen, S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm, Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, In Proceedings of the International Symposium on Computer Architecture, 1996.
20. D. Tullsen and J. Brown, Handling Long-latency Loads in a Simultaneous Multithreading Processor, In Proceedings of the International Symposium on Microarchitecture, 2001.
21. A. El-Moursy and D. H. Albonesi, Front-end Policies for Improved Issue Efficiency in SMT Processors, In Proceedings of the International Symposium on High Performance Computer Architecture, 2003.
22. F. J. Cazorla, E. Fernandez, A. Ramirez, and M. Valero, Dcache Warn: an I-Fetch Policy to Increase SMT Efficiency, In Proceedings of International Parallel and Distributed Processing Symposium, 2004.
23. J. Hasan et al., Heat Stroke: Power-Density-Based Denial of Servie in SMT, In Proceedings of the International Sympoisum on High-Performance Computer Architecture, 2005.
24. T. N. Vijaykumar, I. Pomeranz and K. Cheng, Transient-Fault Recovery via Simultaneous Multithreading, In Proceedings of the International Symposium on Computer Architecture, 2002.
25. S. Reinhardt and S. Mukherjee, Transient Fault Detection via Simultaneous Multithreading, In Proceedings of the International Symposium on Computer Architecture, 2000.