Informed microarchitecture design space exploration using workload dynamics

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 274-285

  Cho, Chang Burm ^a   Zhang, Wangyuan ^a   Li, Tao ^a  

^a UNIVERSITY OF FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE DESIGNS; BILLION (CO); DYNAMIC BEHAVIORS; FORECASTING PERFORMANCE; HIGH ACCURACY; HIGH PERFORMANCE MICROPROCESSORS; INTERNATIONAL SYMPOSIUM; KEY PARAMETERS; MICRO ARCHITECTURE DESIGN; MICRO ARCHITECTURES; MICROPROCESSOR ARCHITECTURES; MULTIRESOLUTION DECOMPOSITION (MRD); NONLINEAR REGRESSION (NLR); PREDICTIVE MODELING; PROGRAM RUNTIME; RUN TIME; WORST-CASE SCENARIO;

ARSENIC COMPOUNDS; BENCHMARKING; CODES (SYMBOLS); DYNAMICS; ELECTRIC LOAD FORECASTING; FOOD PROCESSING; FORECASTING; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; NEURAL NETWORKS; OPTIMIZATION; REDUNDANCY; REGRESSION ANALYSIS; RELIABILITY; SPACE RESEARCH; WAVELET DECOMPOSITION;

ARCHITECTURAL DESIGN;

EID: 47349128440     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.26     Document Type: Conference Paper

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