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Volumn , Issue , 2008, Pages 240-251

Roughness of microarchitectural design topologies and its implications for optimization

Author keywords

[No Author keywords available]

Indexed keywords

CLASSICAL OPTIMIZATIONS; CONTOUR MAPS; DESIGN TOPOLOGIES; GRADIENT ASCENTS; MACHINE LEARNINGS; MICROARCHITECTURAL ANALYSIS; MICROARCHITECTURAL DESIGNS; MULTI-DIMENSIONAL; OPTIMIZATION HEURISTICS; OPTIMIZATION METHODS; REGRESSION MODELS; STATISTICAL INFERENCES;

EID: 57749176188     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2008.4658643     Document Type: Conference Paper
Times cited : (12)

References (20)
  • 3
  • 8
    • 35348870650 scopus 로고    scopus 로고
    • Automated design of application specific superscalar processors: An analytical approach
    • June
    • T. Karkhanis and J. Smith. Automated design of application specific superscalar processors: an analytical approach. In International Symposium on Computer Architecture, June 2007.
    • (2007) International Symposium on Computer Architecture
    • Karkhanis, T.1    Smith, J.2
  • 12
    • 0032683935 scopus 로고    scopus 로고
    • Environment for powerpc microarchitecture exploration
    • May/June
    • M. Moudgill, J. Wellman, and J. Moreno. Environment for powerpc microarchitecture exploration. IEEE Micro, 19(3):9-14, May/June 1999.
    • (1999) IEEE Micro , vol.19 , Issue.3 , pp. 9-14
    • Moudgill, M.1    Wellman, J.2    Moreno, J.3
  • 16
    • 1642330988 scopus 로고    scopus 로고
    • An integrated cache timing, power, and area model
    • Technical Report 2001/2, Compaq Computer Corporation, August
    • P. Shivakumar and N. Jouppi. An integrated cache timing, power, and area model. In Technical Report 2001/2, Compaq Computer Corporation, August 2001.
    • (2001)
    • Shivakumar, P.1    Jouppi, N.2
  • 18
    • 0003720587 scopus 로고    scopus 로고
    • Inherently lower-power high-performance superscalar architectures
    • March
    • V. Zyuban. Inherently lower-power high-performance superscalar architectures. In Ph.D. Thesis, University of Notre Dame, March 2000.
    • (2000) Ph.D. Thesis, University of Notre Dame
    • Zyuban, V.1
  • 20
    • 0348017034 scopus 로고    scopus 로고
    • Balancing hardware intensity in microprocessor pipelines
    • Oct/Nov
    • V. Zyuban and P. Strenski. Balancing hardware intensity in microprocessor pipelines. IBM Journal of Research and Development, 47(5/6), Oct/Nov 2003.
    • (2003) IBM Journal of Research and Development , vol.47 , Issue.5-6
    • Zyuban, V.1    Strenski, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.