메뉴 건너뛰기




Volumn , Issue , 2008, Pages 832-835

Adaptive error control for reliable systems-on-chip

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; ERROR ANALYSIS; PROGRAMMING THEORY; TECHNICAL PRESENTATIONS;

EID: 51749085354     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541547     Document Type: Conference Paper
Times cited : (7)

References (15)
  • 1
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Jan
    • L. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm," Computer, Vol. 35, Issue 1, pp. 70-78, Jan. 2002.
    • (2002) Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 2
    • 84954417739 scopus 로고    scopus 로고
    • Towards on-chip fault-tolerant communication
    • Jan
    • T. Dumitras and R. Marculescu, "Towards on-chip fault-tolerant communication," in Proc. ASP-DAC 2003, pp. 225-232, Jan. 2003.
    • (2003) Proc. ASP-DAC , pp. 225-232
    • Dumitras, T.1    Marculescu, R.2
  • 3
    • 27344448860 scopus 로고    scopus 로고
    • Analysis of error recovery schemes for networks on chip
    • Sept.-Oct
    • S. Murali, et al., "Analysis of error recovery schemes for networks on chip," IEEE Design & Test of Computers, Vol. 22, Issue 5, pp.434-442, Sept.-Oct. 2005.
    • (2005) IEEE Design & Test of Computers , vol.22 , Issue.5 , pp. 434-442
    • Murali, S.1
  • 4
    • 34548130068 scopus 로고    scopus 로고
    • A fault tolerant mechanism for handling permanent and transient failures in a Network on Chip
    • Apr
    • M. Ali, M. Welzl, S. Hessler and S. Hellebrand, "A fault tolerant mechanism for handling permanent and transient failures in a Network on Chip," in Proc ITNG'07, pp. 1027-1032, Apr. 2007.
    • (2007) Proc ITNG'07 , pp. 1027-1032
    • Ali, M.1    Welzl, M.2    Hessler, S.3    Hellebrand, S.4
  • 9
    • 0034245046 scopus 로고    scopus 로고
    • Toward achieving energy efficiency in presence of deep submicron noise
    • Aug
    • R. Hegde and N. R. Shanbhag, "Toward achieving energy efficiency in presence of deep submicron noise," IEEE Trans. Very Large Scale Integration (VLSI) Syst., Vol. 8, No. 4, pp. 379-391, Aug. 2000.
    • (2000) IEEE Trans. Very Large Scale Integration (VLSI) Syst , vol.8 , Issue.4 , pp. 379-391
    • Hegde, R.1    Shanbhag, N.R.2
  • 10
    • 1142287741 scopus 로고    scopus 로고
    • A fault model notation and error-control scheme for switch-to-switch buses in a Network-on-Chip
    • Oct
    • H. Zimmer and A. Jantsch, "A fault model notation and error-control scheme for switch-to-switch buses in a Network-on-Chip," in Proc. CODES+ISSS'03, pp. 188-193, Oct. 2003.
    • (2003) Proc. CODES+ISSS'03 , pp. 188-193
    • Zimmer, H.1    Jantsch, A.2
  • 11
    • 51749086678 scopus 로고    scopus 로고
    • http://www.eas.asu.edu/~ptm/
  • 12
    • 33745715755 scopus 로고    scopus 로고
    • Power analysis of link level and end-to-end data protection in networks on chip
    • May
    • A. Jantsch, R. Lauter and A. Vitkowski, " Power analysis of link level and end-to-end data protection in networks on chip," in Proc. ISCAS'05, pp. 1770-1773, May 2005.
    • (2005) Proc. ISCAS'05 , pp. 1770-1773
    • Jantsch, A.1    Lauter, R.2    Vitkowski, A.3
  • 13
    • 34250849255 scopus 로고    scopus 로고
    • Online reconfigurable self-timed links for fault tolerant
    • Article ID 94676, pp
    • T. Lehtonen, P. Liljeberg, and J. Plosila, "Online reconfigurable self-timed links for fault tolerant NoC," VLSI Design, Vol 2007, Article ID 94676, pp.1-13, 2007.
    • (2007) VLSI Design , vol.2007 , pp. 1-13
    • Lehtonen, T.1    Liljeberg, P.2    Plosila, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.