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1
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0036149420
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Networks on chips: A new SoC paradigm
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Jan
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L. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm," Computer, Vol. 35, Issue 1, pp. 70-78, Jan. 2002.
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(2002)
Computer
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Benini, L.1
De Micheli, G.2
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2
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84954417739
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Towards on-chip fault-tolerant communication
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Jan
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T. Dumitras and R. Marculescu, "Towards on-chip fault-tolerant communication," in Proc. ASP-DAC 2003, pp. 225-232, Jan. 2003.
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Proc. ASP-DAC
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Dumitras, T.1
Marculescu, R.2
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3
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27344448860
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Analysis of error recovery schemes for networks on chip
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Sept.-Oct
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S. Murali, et al., "Analysis of error recovery schemes for networks on chip," IEEE Design & Test of Computers, Vol. 22, Issue 5, pp.434-442, Sept.-Oct. 2005.
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IEEE Design & Test of Computers
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Murali, S.1
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4
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A fault tolerant mechanism for handling permanent and transient failures in a Network on Chip
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Apr
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M. Ali, M. Welzl, S. Hessler and S. Hellebrand, "A fault tolerant mechanism for handling permanent and transient failures in a Network on Chip," in Proc ITNG'07, pp. 1027-1032, Apr. 2007.
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Proc ITNG'07
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Ali, M.1
Welzl, M.2
Hessler, S.3
Hellebrand, S.4
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5
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20444467586
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Error control scheme for on-chip communication links: The energy-reliability tradeoff
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Jun
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D. Bertozzi, L. Benini, and G. De Micheli, "Error control scheme for on-chip communication links: the energy-reliability tradeoff," IEEE Trans. Compuater-Aided Design of Integrated. Circuits and Syst., Vol. 24, No. 6, pp. 818-831, Jun. 2005.
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IEEE Trans. Compuater-Aided Design of Integrated. Circuits and Syst
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Bertozzi, D.1
Benini, L.2
De Micheli, G.3
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6
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23744468720
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Coding for system-on-chip networks: A unified framework
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June
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Srinivasa R. Sridhara, and Naresh R. Shanbhag, "Coding for system-on-chip networks: A unified framework," IEEE Trans. Very Large Scale Integration (VLSI) Syst.,Vol. 13, pp. 655-667, June 2006.
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Sridhara, S.R.1
Shanbhag, N.R.2
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7
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16244381883
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A robust self-calibrating transmission scheme for on-chip networks
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Dec
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F. Worm, P. Ienne, P. Thiran and G. De Micheli, "A robust self-calibrating transmission scheme for on-chip networks," IEEE Trans. Very Large Scale Integration (VLSI) Syst.,, Vol. 12, No. 12, pp. 1360-1373, Dec. 2004.
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IEEE Trans. Very Large Scale Integration (VLSI) Syst
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Worm, F.1
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8
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Self-calibrating networks-on-chip
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May
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F. Worm, P. Thiran, G. De Micheli and P. Ienne, "Self-calibrating networks-on-chip," in Proc. ISCAS'05, pp. 2361-2364, May 2005.
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Proc. ISCAS'05
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Worm, F.1
Thiran, P.2
De Micheli, G.3
Ienne, P.4
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9
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0034245046
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Toward achieving energy efficiency in presence of deep submicron noise
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Aug
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R. Hegde and N. R. Shanbhag, "Toward achieving energy efficiency in presence of deep submicron noise," IEEE Trans. Very Large Scale Integration (VLSI) Syst., Vol. 8, No. 4, pp. 379-391, Aug. 2000.
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Hegde, R.1
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A fault model notation and error-control scheme for switch-to-switch buses in a Network-on-Chip
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Oct
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H. Zimmer and A. Jantsch, "A fault model notation and error-control scheme for switch-to-switch buses in a Network-on-Chip," in Proc. CODES+ISSS'03, pp. 188-193, Oct. 2003.
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Zimmer, H.1
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12
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33745715755
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Power analysis of link level and end-to-end data protection in networks on chip
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May
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A. Jantsch, R. Lauter and A. Vitkowski, " Power analysis of link level and end-to-end data protection in networks on chip," in Proc. ISCAS'05, pp. 1770-1773, May 2005.
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Jantsch, A.1
Lauter, R.2
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13
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Online reconfigurable self-timed links for fault tolerant
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Article ID 94676, pp
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T. Lehtonen, P. Liljeberg, and J. Plosila, "Online reconfigurable self-timed links for fault tolerant NoC," VLSI Design, Vol 2007, Article ID 94676, pp.1-13, 2007.
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VLSI Design
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Lehtonen, T.1
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14
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Morgan Kaufmann, Chapter 4, pp
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G. De Micheli and L. Benini, NetWorks On Chips, Morgan Kaufmann, Chapter 4, pp. 81-90, 2007.
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NetWorks On Chips
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De Micheli, G.1
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15
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0347409250
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Adaptive error protection for energy efficiency
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Nov
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L. Li, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, "Adaptive error protection for energy efficiency," in Proc. ICCAD'03, pp. 2-7, Nov. 2003.
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Proc. ICCAD'03
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Li, L.1
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