Modeling effects of interface traps on the gate C-V characteristics of MOS devices on alternative high-mobility substrates

Solid-State Electronics

Volumn 54, Issue 6, 2010, Pages 621-627

  Satter, Md Mahbub ^a   Haque, Anisul ^b  

^a BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY   (Bangladesh)

^b EAST WEST UNIVERSITY   (Bangladesh)

Author keywords

Dit extraction; High mobility substrate; Interface trap states; MOS gate C V modeling; Quantum mechanical effect

Indexed keywords

HIGH MOBILITY; MOS GATES; QUANTUM MECHANICAL EFFECT; QUANTUM MECHANICAL EFFECTS; SUBSTRATE INTERFACE;

GATE DIELECTRICS; GATES (TRANSISTOR); GERMANIUM; NUMERICAL ANALYSIS; POISSON EQUATION; SEMICONDUCTING SILICON; SUBSTRATES; WAVE EQUATIONS; WAVE FUNCTIONS;

MOS DEVICES;

EID: 77950209877     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2010.02.004     Document Type: Article

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