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Volumn 6, Issue 1, 2010, Pages

Routing in self-organizing nano-scale irregular networks

Author keywords

Data parallel; DNA; Nanocomputing; Self organizing; SIMD

Indexed keywords

ABUNDANT RESOURCES; CMOS TECHNOLOGY; COMMUNICATION LATENCY; DATA PARALLEL; DEADLOCK FREE; DEFECT TOLERANCE; EULER PATH; EXECUTION TIME; FABRICATION DEFECTS; IRREGULAR NETWORKS; IRREGULAR TOPOLOGY; NANO SCALE; NANO-COMPUTING; ON-CHIP NETWORKS; PHYSICAL TOPOLOGY; RESOURCE-CONSTRAINED; ROUTING APPROACH; ROUTING TECHNIQUES; SELF ORGANIZING; SHORTEST PATH; SILICON PLATFORMS; SIMD ARCHITECTURE; STATIC ROUTING ALGORITHM;

EID: 77949551944     PISSN: 15504832     EISSN: 15504840     Source Type: Journal    
DOI: 10.1145/1721650.1721653     Document Type: Article
Times cited : (6)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.