Design of high-throughput fully parallel LDPC decoders based on wire partitioning

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 3, 2010, Pages 482-489

  Onizawa, Naoya ^a   Hanyu, Takahiro ^a   Gaudet, Vincent C ^b  

^a TOHOKU UNIVERSITY   (Japan)

^b UNIVERSITY OF ALBERTA   (Canada)

Author keywords

Forward error control (FEC); Iterative decoding; Low density parity check (LDPC) codes; VLSI

Indexed keywords

BIT ERROR RATE PERFORMANCE; CLOCK CYCLES; CMOS TECHNOLOGY; CODE-WORDS; CRITICAL PATH DELAYS; DESIGN FLOWS; ENERGY CONSUMPTION; ENERGY-PER-BIT; FORWARD ERROR CONTROL (FEC); FORWARD ERROR CONTROLS; HIGH-THROUGHPUT; IN-CORE; LDPC CODES; LDPC DECODER; LOG LIKELIHOOD RATIO; LOW DENSITY PARITY CHECK; LOW-DENSITY PARITY-CHECK CODES; PIPELINE REGISTERS; PLACEMENT AND ROUTING; POST LAYOUT SIMULATION; UNCODED;

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); CODING ERRORS; MAXIMUM LIKELIHOOD ESTIMATION; THROUGHPUT; WIRE;

ITERATIVE DECODING;

EID: 77649191580     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2011360     Document Type: Article

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