High throughput low-density parity-check decoder architectures

Conference Record / IEEE Global Telecommunications Conference

Volumn 5, Issue , 2001, Pages 3019-3024

  Yeo, Engling ^a   Pakzad, Payam ^a   Nikolić, Borivoje ^a   Anantharam, Venkat ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); GRAPH THEORY; MAGNETIC RECORDING;

LOW DENSITY PARITY CHECK DECODERS;

DECODING;

EID: 0035685606     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Near Shannon limit performance of low density parity check codes
2. VLSI architectures for iterative decoders in magnetic recording channels
3. A recursive approach to low complexity codes
4. Low density parity check codes based on finite geometries: A rediscovery
5. Constrained coding techniques for soft iterative decoders
6. A 220mW 1-Gbit/s 1024-Bit Rate-1/2 low density parity check code decoder
7. Optimizing the mapping of low-density parity check codes on parallel decoding architectures
8. The generalized distributive law