A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 459-462

  Darabiha, Ahmad ^a   Carusone, Anthony Chan ^a   Kschischang, Frank R ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; FORWARD ERROR CORRECTION; INTEGRATED CIRCUITS; VOLTAGE SCALING;

BIT-SERIAL; BIT-SERIAL ARCHITECTURE; EARLY TERMINATION; LDPC DECODER; LDPC DECODING; MULTI-GBPS; ROUTING CONGESTION; SUPPLY-VOLTAGE SCALING;

DECODING;

EID: 84938574768     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405773     Document Type: Conference Paper

References (8)

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