3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm

Midwest Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 217-220

  Onizawa, Naoya ^a   Ikeda, Tomokazu ^a   Hanyu, Takahiro ^a   Gaudet, Vincent C ^b  

^a TOHOKU UNIVERSITY   (Japan)

^b UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER NETWORKS;

LDPC DECODERS; LDPC DECODING; LOW-DENSITY-PARITY CHECK; SYSTEM CLOCKS;

DECODING;

EID: 51449118414     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2007.4488574     Document Type: Conference Paper

References (9)

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