A scalable LDPC decoder ASIC architecture with bit-serial message exchange

Integration, the VLSI Journal

Volumn 41, Issue 3, 2008, Pages 385-398

  Brandon, Tyler ^a   Hang, Robert ^a   Block, Gary ^a   Gaudet, Vincent C ^a   Cockburn, Bruce ^a   Howard, Sheryl ^a   Giasson, Christian ^a   Boyle, Keith ^a   Goud, Paul ^a   Zeinoddin, Siavash Sheikh ^a   Rapley, Anthony ^a   Bates, Stephen ^a   Elliott, Duncan ^a   Schlegel, Christian ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

Bit serial arithmetic; Error control codes; Iterative decoding; Low density parity check codes

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECODING; ENERGY EFFICIENCY; ITERATIVE METHODS; MESSAGE PASSING; SIGNAL TO NOISE RATIO;

DECODING ALGORITHMS; EXTRINSIC MESSAGES; LOW-DENSITY PARITY CHECK (LDPC); PARITY CHECK NODE PROCESSING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 43049181464     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2007.07.003     Document Type: Article

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