An 8.29 mm2 52 mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13 μm CMOS process

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 3, 2008, Pages 672-683

  Shih, Xin Yu ^a   Zhan, Cheng Zhou ^a   Lin, Cheng Hung ^a   Wu, An Yeu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

LDPC codes; Low power and early termination; Mobile WiMAX; Multi mode design

Indexed keywords

COMPUTATIONAL METHODS; DECODING; ENERGY DISSIPATION; LOGIC DESIGN;

DECODING LATENCY; MOBILE WIMAX; MULTIMODE DESIGN;

CMOS INTEGRATED CIRCUITS;

EID: 40149092390     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.916606     Document Type: Article

References (26)

1. R. Gallager, "Low-density parity-check codes," IRE Trans. Inf. Theory, vol. 7, pp. 21-28, Jan. 1962.
2. D. J. C. MacKay, "Good error-correcting codes based on very sparse matrices," IEEE Trans. Inf. Theory, vol. 45, no. 3, pp. 399-431, Jan. 1999.
3. C. J. Howland and A. J. Blanksby, "Parallel decoding architectures for low density parity check codes," in Proc. IEEE ISCAS, May 2001, vol. 4, pp. 742-745.
4. Z. Cui and Z. Wang, "Area-efficient parallel decoder architecture for high rate QC-LDPC codes," in Proc. IEEE ISCAS, May 2006, pp. 5107-5110.
5. M. Cocco, J. Dielissen, M. Heijligers, A. Hekstra, and J. Huisken, "A scalable architecture for LDPC decoding," in Proc. IEEE Conf. Design Automation and Test in Europe (DATE), Feb. 2004, vol. 3, pp. 88-93.
6. E. Yeo, B. Nikolic, and V. Anantharam, "Architectures and implementations of low-density parity-check decoding algorithms." in Proc. Midwest Symp. Circuits and Systems, Aug. 2002, vol. 3, pp. 437-440.
7. IEEE 802.16e. [Online]. Available: http://www.ieee802.org/16/tge/
8. WiMAX Forum. [Online]. Available: http://www.wimaxforum.org/home
9. R. M. Tanner, "A recursive approach to low complexity codes," IEEE Trans. Inf. Theory, vol. IT-27, no. 5, pp. 399-431, Sep. 1981.
10. F. R. Kschischang, B. J. Frey, and H. A. Loeliger, "Factor graphs and the sum-product algorithm," IEEE Trans. Inf. Theory, vol. 47, pp. 498-519, Feb. 2001.
11. J. M. F. Moura, J. Lu, and H. Zhang, "Structured low-density parity-check codes," IEEE Signal Process. Mag., vol. 21, no. 1, pp. 42-55, Jan. 2004.
12. E. Yeo, B. Nikolic, and V. Anantharam, "Iterative decoder architectures," IEEE Commun. Mag., vol. 41, pp. 132-140, Aug. 2003.
13. H. Zhong and T. Zhang, "Design of VLSI implementation-oriented LDPC codes," in Proc. IEEE 58th Vehicular Technology Conf., Oct. 2003, vol. 1, pp. 670-673.
14. S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, 2nd ed. New York: Pearson/Prentice Hall. 2004.
15. I. C. Park and S. H. Kang, "Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation," in Proc. IEEE ISCAS, May 2005, pp. 5778-5781.
16. T. Zhang and K. K. Parhi, "VLSI Implementation-oriented (3,k)-regular low-density parity-check codes." in IEEE Workshop on Signal Processing Systems (SiPS), Sep. 2001, pp. 25-36.
17. Y. Chen and K. K. Parhi, "Overlapped message passing for quasi-cyclic low density parity check codes," IEEE Trans. Circuits Syst., vol. 51, pp. 1106-1113, Jun. 2004.
18. S. Kim and K. K. Parhi, "Overlapped decoding for a class of quasi-cyclic codes," in Proc. IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2004, pp. 113-117.
19. J. Li, X. H. You, and J. Li, "Early stopping for LDPC decoding: Convergence of Mean Magnitude (CMM)," IEEE Commun. Lett., vol. 10, no. 9, pp. 667-669, Sep. 2006.
20. F. Kienle and N. Wehn, "Low complexity stopping criterion for LDPC code decoders," in Proc. 2005 IEEE Vehicular Technology Conf., May 2005, vol. 1, pp. 606-609.
21. R. Y. Shao, S. Lin, and M. P. C. Fossorier, "Two simple stopping criteria for turbo decoding," IEEE Trans. Commun., vol. 47, no. 8, pp. 1117-1120, Oct. 2002.
22. A. J. Blanksby and C. J. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE J. Solid-State Circuits, vol. 37, pp. 404-412, Mar. 2002.
23. A. Darabiha, A. C. Carusone, and F. R. Kschischang, "Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity," in Proc. IEEE ISCAS, May 2005, vol. 5, pp. 5194-5197.
24. M. M. Mansour and N. R. Shanbhag, "A 640-Mb/s 2048-bit programmable LDPC decoder chip," IEEE J. Solid-State Circuits, vol. 41, pp. 684-698, Mar. 2006.
25. S. H. Kang and I. C. Park, "Loosely coupled memory-based decoding architecture for low density parity check codes," IEEE Trans. Circuits Syst. I, vol. 53, no. 5, pp. 1045-1056, May 2006.
26. 2 52-mW LDPC decoder chip for IEEE 802.16e system," in Proc. Int. Symp. VLSI Circuits and VLSI Technology (SOVC-2007), Kyoto, Japan, Jun. 2007, pp. 16-17.