IBM POWER6 reliability

IBM Journal of Research and Development

Volumn 51, Issue 6, 2007, Pages 763-774

  Mack, Michael J ^a   Sauer, Wolfram M ^a   Swaney, Scott B ^a   Mealey, Bruce G ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; STORAGE ALLOCATION (COMPUTER);

INSTRUCTION RETRY RECOVERY; INSTRUCTION SET ARCHITECTURE; MAINFRAME SYSTEM;

MICROPROCESSOR CHIPS;

EID: 37549059932     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/rd.516.0763     Document Type: Article

References (5)

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3. H. Ando, Y. Yoshida, A. Inoue, I. Sugiyama, T. Asakawa, K. Morita, T. Muta, et al., "A 1.3-GRz Fifth-Generation SPARC64 Microprocessor," IEEE J. Solid-State Circuits 38, No. 11, 1896-1905 (2003).
4. M. Mueller, L. C. Alves, W. Fischer, M. L. Fair, and I. Modi, "RAS Strategy for IBM S/390 G5 and G6," IBM J. Res. & Dev. 43, No. 5/6, 875-888 (1999).
5. D. C. Bossen, A. Kitamorn, K. F. Reick, and M. S. Floyd, "Fault-Tolerant Design of the IBM pSeries 690 System Using POWER4 Processor Technology," IBM J. Res. & Dev. 46, No. 1, 77-86 (2002).