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Volumn , Issue , 2008, Pages 113-153

BSIM-CMG: A compact model for multi-gate transistors

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[No Author keywords available]

Indexed keywords


EID: 76449114880     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-0-387-71752-4_3     Document Type: Chapter
Times cited : (58)

References (22)
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    • H.-S.P. Wong, D.J. Frank, P.M. Solomon: Device Design Considerations for Double-Gate, Ground Plane and Single-Gate Ultra-Thin SOI MOSFETs at the 25nm Channel Length Generation. IEDM Tech. Digest, 407 (1998).
    • (1998) IEDM Tech. Digest , pp. 407
    • Wong, H.-S.P.1    Frank, D.J.2    Solomon, P.M.3
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    • Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate mosfets
    • Y. Taur: Analytic Solutions of Charge and Capacitance in Symmetric and Asymmetric Double-Gate MOSFETs. IEEE Trans. Electron Devices 48, 2861 (2001).
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    • Taur, Y.1
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    • A design-oriented charge-based current model for symmetric dg mosfet and its correlation with the ekv formalism
    • J.-M. Sallese, F. Krummenacher, F. Pregaldiny, C. Lallement, A. Roy, C. Enz: A design-oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism. Solid-State Electronics 49, 485 (2005).
    • (2005) Solid-State Electronics , vol.49 , pp. 485
    • Sallese, J.-M.1    Krummenacher, F.2    Pregaldiny, F.3    Lallement, C.4    Roy, A.5    Enz, C.6
  • 10
    • 0017932965 scopus 로고
    • A charge sheet model of the mosfet
    • J. R. Brews: A charge sheet model of the MOSFET. Solid-State Electronics 21, 345 (1978).
    • (1978) Solid-State Electronics , vol.21 , pp. 345
    • Brews, J.R.1
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    • 0018027059 scopus 로고
    • A charge-oriented model for mos transistor capacitances
    • D. Ward, R. Dutton: A charge-oriented model for MOS transistor capacitances. IEEE J. Solid State Circuits 13, 703 (1978).
    • (1978) IEEE J. Solid State Circuits , vol.13 , pp. 703
    • Ward, D.1    Dutton, R.2
  • 12
    • 0000098111 scopus 로고    scopus 로고
    • Dc electrical oxide thickness model for quantization of the inversion layer in mosfets
    • Y. King, H. Fujioka, S. Kamohara, K. Chen, C. Hu: DC electrical oxide thickness model for quantization of the inversion layer in MOSFETs. Semicond. Sci. Technol. 13, 963 (1998).
    • (1998) Semicond. Sci. Technol. , vol.13 , pp. 963
    • King, Y.1    Fujioka, H.2    Kamohara, S.3    Chen, K.4    Hu, C.5
  • 13
    • 0032070926 scopus 로고    scopus 로고
    • Semiconductor thickness effects in the double-gate soi mosfet
    • B. Majkusiak, T. Janik, J. Walczak: Semiconductor thickness effects in the double-gate SOI MOSFET. IEEE Trans. Electron Devices 45, 1127 (1998).
    • (1998) IEEE Trans. Electron Devices , vol.45 , pp. 1127
    • Majkusiak, B.1    Janik, T.2    Walczak, J.3
  • 14
    • 0036475197 scopus 로고    scopus 로고
    • Modeling of quantization and volume inversion in thin si-film double-gate mosfets
    • L. Ge, J. Fossum: Modeling of Quantization and Volume Inversion in Thin Si-Film Double-Gate MOSFETs. IEEE Trans. Electron Devices, 49, 287 (2002).
    • (2002) IEEE Trans. Electron Devices , vol.49 , pp. 287
    • Ge, L.1    Fossum, J.2
  • 15
    • 23844491449 scopus 로고    scopus 로고
    • Quantum-mechanical effects on the threshold voltage of undoped double-gate mosfets
    • V. Trivedi, J. Fossum: Quantum-Mechanical Effects on the Threshold Voltage of Undoped Double-Gate MOSFETs. IEEE Electron Devices Lett. 26, 579 (2005).
    • (2005) IEEE Electron Devices Lett , vol.26 , pp. 579
    • Trivedi, V.1    Fossum, J.2
  • 16
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    • A unified quantum correction model for nanoscale singleand double-gate mosfets under inversion conditions
    • Y. Li, S.-M. Yu: A unified quantum correction model for nanoscale singleand double-gate MOSFETs under inversion conditions. Nanotechnology 15, 1009 (2004).
    • (2004) Nanotechnology , vol.15 , pp. 1009
    • Li, Y.1    Yu, S.-M.2
  • 19
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    • A 2-d analytical solution for sces in dg mosfets
    • X. Liang, Y. Taur: A 2-D Analytical Solution for SCEs in DG MOSFETs. IEEE Trans. Electron Devices 51, 1385 (2004).
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    • Liang, X.1    Taur, Y.2
  • 22
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    • An analytic potential model for symmetric and asymmetric dg mosfets
    • H. Lu, Y. Taur: An Analytic Potential Model for Symmetric and Asymmetric DG MOSFETs. IEEE Trans. Electron Devices 53, 1161 (2006).
    • (2006) IEEE Trans. Electron Devices , vol.53 , pp. 1161
    • Lu, H.1    Taur, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.