Synthesizing reversible circuits for irreversible functions

12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

Volumn , Issue , 2009, Pages 749-756

  Miller, D Michael ^a   Wille, Robert ^b   Dueck, Gerhard W ^c  

^a UNIVERSITY OF VICTORIA   (Canada)

^b UNIVERSITY OF BREMEN   (Germany)

^c UNIVERSITY OF NEW BRUNSWICK   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BENCH-MARK PROBLEMS; COMMON FEATURES; REVERSIBLE CIRCUITS;

SPECIFICATIONS;

SYNTHESIS (CHEMICAL);

EID: 74549155832     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2009.186     Document Type: Conference Paper

References (30)

1. V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, "Reversible logic circuit synthesis," in Proc. Int'l Conf. on CAD, 2002, pp. 125-132.
2. A. Agrawal and N. Jha, "Reversible logic synthesis," in Proc. Design, Automation and Test in Europe, 2004, pp. 1384-1385.
3. J. Donald and N. K. Jha, "Reversible logic synthesis with Fredkin and Peres gates," J. Emergin Technology Computing Systems, vol. 4, no. 1, pp. 1-19, 2008.
4. P. Gupta, A. Agrawal, and N. K. Jha, "An algorithm for synthesis of reversible logic circuits," IEEE Trans. on CAD, vol. 25, no. 11, pp. 2317-2330, Nov. 2006.
5. Z. Guan, X. Qin, Z. Ge, and Y. Zhang, "Reversible synthesis with minimum logic function," in Proc. Conf. on Computational Intelligence and Security, vol. 2, 2006, pp. 968-971.
6. P. Kerntopf, "A new heuristic algorithm for reversible logic synthesis," in Proc. Design Automation Conf., 2004, pp. 834-837.
7. D. M. Miller, D. Maslov, and G. W. Dueck, "A transformation based algorithm for reversible logic synthesis," in Proc. Design Automation Conf., 2003, pp. 318-323.
8. D. Maslov, G. W. Dueck, and D. M. Miller, "Techniques for the synthesis of reversible Toffoli networks," ACM Trans. Des. Autom. Electron. Syst., vol. 12, no. 4, pp. 42.1-42.28, 2007.
9. D. Maslov and D. M. Miller, "Reed-Muller spectra based synthesis of reversible circuits using a quantum cost metric," in 7th International Symposium on Representations and Methodology of Future Computing Technologies (RM), 2005.
10. M. Saeedi, M. Sedighi, and M. S. Zamani, "A novel synthesis algorithm for reversible circuits," in Proc. Int'l Conf. on CAD, 2007, pp. 65-68.
11. M. Saeedi, M. S. Zamani, and M. Sedighi, "On the behavior of substitution-based reversible circuit synthesis algorithms: Investigation and improvement," in Proc. IEEE Computer Society Symp. on VLSI, 2007, pp. 428-436.
12. K. Fazel, M. Thornton, and J. E. Rice, "ESOP-based Toffoli gate cascade generation," in Proceedings IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), 2007, pp. 206-209.
13. Z. Sasanian, M. Saeedi, M. Sedighi, and M. Zamani, "A cycle-based synthesis algorithm for reversible logic," in Proc. ASP Design Automation Conf., 2009, pp. 745-750.
14. Y. Zheng and C. Huang, "A novel Toffoli network synthesis algorithm for reversible logic," in Proc. ASP Design Automation Conf., 2009, pp. 739-744.
15. M. Saeedi, M. S. Zamani, and M. Sedighi, "Algebraic characterization of CNOT-baed quantum circuits with its application to logic synthesis," in Proc. European Conf. on Digital Systems Design, 2007, pp. 339-346.
16. D. Yuan, B. Yan, L. WenTao, and G. Yi, "Research and implementation of reversible logic synthesis algorithm in digital system," in Proc. Computer-Aided Indust. Design and Conceptual Design, 2006, pp. 1-7.
17. M. Mohammadi and M. Eshghi, "Heuristic methods to use don't-cares in automated design of reversible and quantum logic circuits," Quantum Information Processing, vol. 7, pp. 175-192, 2008.
18. D. Maslov and G. W. Dueck, "Reversible cascades with minimal garbage." IEEE Trans. on CAD, vol. 23, no. 11, pp. 1497-1509, 2004.
19. R. Wille and D. Große, "Fast exact Toffoli network synthesis of reversible logic," in Proc. Int'l Conf. on CAD, 2007, pp. 60-64.
20. M. Nielsen and I. Chuang, Quantum Computation and Quantum Information. Cambridge Univ. Press, 2000.
21. A. Barenco, C. Bennett, R. Cleve, D. DiVinchenzo, N. Margolus, P. Shor, T. Sleator, J. Smolin, and H. Weinfurter, "Elementary gates for quantum computation," Physical Review A, vol. 52, pp. 3457-3467, 1995.
22. D. Maslov, C. Young, D. M. Miller, and G. W. Dueck, "Quantum circuit simplification using templates," in Proc. Design, Automation and Test in Europe, 2005, pp. 1208-1213.
23. F. S. Hillier and G. J. Lieberman, Introduction to Operations Research. McGraw-Hill Professional, 2005.
24. D. Maslov, "Reversible logic synthesis," Ph.D. dissertation, University of New Brunswick, 2003.
25. D. M. Miller and G. W. Dueck, "Spectral techniques for reversible logic synthesis," in 6th Int. Symp. on Representations and Methodology of Future Computing Technologies, 2003, pp. 56-62.
26. K. Iwama, Y. Kambayashi, and S. Yamashita, "Transformation rules for designing CNOT-based quantum circuits," in Proc. Design Automation Conf., 2002, pp. 419-424.
27. D. Maslov, G. W. Dueck, and D. M. Miller, "Fredkin/Toffoli templates for reversible logic synthesis," in Proc. Int'l Conf. on CAD, 2003, pp. 256-261.
28. G. W. Dueck and D. Maslov, "Generation of multiple-control Toffoli network templates," in Proc. Int'l Workshop on Logic Synthesis, 2007, pp. 39-44.
29. R. Wille, D. Große, G. W. Dueck, and R. Drechsler, "Reversible logic synthesis with output permutation," in Proc. Int'l Conf. on VLSI Design, 2009, pp. 189-194.
30. R. Wille, D. Große, L. Teuber, G. W. Dueck, and R. Drechsler, "RevLib: An online resource for reversible functions and reversible circuits," in Int'l Symp. on Multi-Valued Logic, 2008, pp. 220-225, RevLib is available at www.revlib.org.