SCOPUS 정보 검색 플랫폼

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 1384-1385

Synthesis of reversible logic

(2) Agrawal, Abhinav a Jha, Niraj K a

a Princeton University (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INPUT OUTPUT VECTOR MAPPING; POSITIVE POLARITY REED-MULLER (PPRM) EXPANSION; REVERSIBLE FUNCTIONS; REVERSIBLE LOGIC; LOGIC SYNTHESIS; LOW-POWER DESIGN; OUTPUT VECTORS; PRIORITY QUEUES; QUANTUM COMPUTING; REVERSIBLE CIRCUITS; SYNTHESIS ALGORITHMS;

ADDERS; ALGORITHMS; COMPUTER CIRCUITS; COMPUTER SIMULATION; PROGRAM PROCESSORS; RANDOM ACCESS STORAGE; ELECTRIC POWER SUPPLIES TO APPARATUS; QUANTUM COMPUTERS;

FORMAL LOGIC; EXHIBITIONS;

EID: 3042515336 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/DATE.2004.1269099 Document Type: Conference Paper

Times cited : (55)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.