A new heuristic algorithm for reversible logic synthesis

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 834-837

  Kerntopf, Pawel ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Reversible Logic Circuits; Synthesis

Indexed keywords

COSTS; DECISION THEORY; DIGITAL SIGNAL PROCESSING; HEURISTIC METHODS; LOGIC GATES; QUANTUM THEORY;

BINARY DECISION DIAGRAMS (BDD); FREDKIN GATES; IRREVERSIBLE GATES; REVERSIBLE LOGIC CIRCUITS;

LOGIC CIRCUITS;

EID: 4444239912     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996789     Document Type: Conference Paper

References (17)

1. Agrawal, A., Jha, N. K. Synthesis of reversible logic. In Proc. Design and Test in Europe Conference, Paris, France, February 2004, 1384-1385.
2. Dueck, G. W., Maslov, D., and Miller, D. M. Transformation-based synthesis of networks of Toffoli/Fredkin gates. In IEEE Canadian Conference on Electrical and Computer Engineering, Montreal, Canada, May 2003.
3. Iwama, K., Kambayashi, Y., and Yamashita, S. Transformation rules for designing CNOT-based quantum circuits. In Proc. Design Automation Conference, New Orleans, LA, June 2002, 419-425.
4. Kerntopf, P. An approach to minimization of decision diagrams. In Proc. EUROMICRO Symposium on Digital Systems Design, Warsaw, Poland, Sept. 2001, 79-86.
5. th International Symposium on Representations and Methodology of Future Computing Technology, Trier, Germany, March 2003, 183-190.
6. th IEEE/ACM International Workshop on Logic and Synthesis, New Orleans, LA, June 2002, 261-266.
7. th International Symposium on Representations and Methodology of Future Computing Technology, Trier, Germany, March 2003, 162-170.
8. th IEEE/ACM International Workshop on Logic and Synthesis, Laguna Beach, CA, May 2003, 226-230.
9. th IEEE/ACM International Workshop on Logic and Synthesis, Laguna Beach, CA, June 2003, 320-325.
10. th Symposium on Integrated Circuits and System Design, Sao Paulo, Brazil, Sept. 2003.
11. Maslov, D., Dueck, G. W., and Miller, D. M. Fredkin/Toffoli templates for reversible logic synthesis. Proc. International Conference on Computer-Aided Design, San Jose, CA, Nov. 2003.
12. th International Symposium on Representations and Methodology of Future Computing Technology, Trier, Germany, March 2003, 56-62.
13. Miller, D. M., Maslov, D., and Dueck, G. W. A transformation based algorithm for reversible logic synthesis. Proc. Design Automation Conference, Anaheim, CA, June 2003, 318-323.
14. th IEEE/ACM International Workshop on Logic and Synthesis, New Orleans, LA, June 2002, 197-202.
15. th International Workshop on Applications of Reed-Muller Expansion in Circuit Design, Starkville, MS, Aug. 2001, 119-138.
16. Shende, V. V., Prasad, A. K., Markov, I. L., and Hayes, J. P. Reversible logic circuit synthesis. IEEE Trans. CAD, 22, 6 (June 2003), 710-722.
17. Sasao, T., and Fujita, M. (eds.) Representations of Discrete Functions, Kluwer Academic Publishers, 1996.