ESOP-based Toffoli gate cascade generation

IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings

Volumn , Issue , 2007, Pages 206-209

  Fazel, K ^a   Thornton, M A ^a   Rice, J E ^b  

^a Southern Methodist University   (United States)

^b UNIVERSITY OF LETHBRIDGE   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; HEURISTIC ALGORITHMS; RECURSIVE FUNCTIONS; SIGNAL PROCESSING;

CASCADE (CO); CASCADE SYNTHESIS; COST METRIC; DIVIDE-AND-CONQUER (DAC); GATE PLACEMENT; LOGIC FUNCTIONS; PACIFIC RIM; REVERSIBLE GATES;

HEURISTIC PROGRAMMING;

EID: 47349095028     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACRIM.2007.4313212     Document Type: Conference Paper

References (9)

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4. V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, "Synthesis of Reversible Logic Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 22(6), pp. 710-722, (June 2003).
5. B. Steinbach and A. Mishchenko, "SNF: a Special Normal Form for ESOPs," Proc. Reed-Muller Workshop, pp. 66-81, 2001.
6. P. Gupta, A. Agrawal, and N. K. Jha. "An Algorithm for Synthesis of Reversible Logic Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 25(11), pp. 2317-2330, (Nov. 2006).
7. th International Workshop on Post-Binary ULSI Systems, Tokyo, May 2003 (downloaded Mar. 2007 from http://www.cs.unb.ca/profs/gdueckreversible/esop.pdf).
8. th International Symposium on Representations and Methodology of Future Computing Technology, (RM), pp. 144-153, 2003
9. th International Reed-Muller Workshop, pp. 242-250, 2001.