-
1
-
-
0036931972
-
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm 2 SRAM cell
-
S. E. Thompson, N. Anand, M. Armstrong, C. Auth, B. Arcot, M. Alavi, P. Bai, J. Bielefeld, R. Bigwood, J. Brandenburg, M. Buehler, S. Cea, V. Chikarmane, C. Choi, R. Frankovic, T. Ghani, G. Glass, W. Han, T. Hoffmann, M. Hussein, P. Jacob, A. Jain, C. Jan, S. Joshi, C. Kenyon, J. Klaus, S. Klopcic, J. Luce, Z. Ma, B. McIntyre, K. Mistry, A. Murthy, P. Nguyen, H. Pearson, T. Sandford, R. Schweinfurth, R. Shaheed, S. Sivakumar, M. Taylor, B. Tufts, C. Wallace, P. Wang, C. Weber, and M. Bohr, "A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm 2 SRAM cell" in IEDM Tech. Dig., 2002, pp. 61-64.
-
(2002)
IEDM Tech. Dig.
, pp. 61-64
-
-
Thompson, S.E.1
Anand, N.2
Armstrong, M.3
Auth, C.4
Arcot, B.5
Alavi, M.6
Bai, P.7
Bielefeld, J.8
Bigwood, R.9
Brandenburg, J.10
Buehler, M.11
Cea, S.12
Chikarmane, V.13
Choi, C.14
Frankovic, R.15
Ghani, T.16
Glass, G.17
Han, W.18
Hoffmann, T.19
Hussein, M.20
Jacob, P.21
Jain, A.22
Jan, C.23
Joshi, S.24
Kenyon, C.25
Klaus, J.26
Klopcic, S.27
Luce, J.28
Ma, Z.29
McIntyre, B.30
Mistry, K.31
Murthy, A.32
Nguyen, P.33
Pearson, H.34
Sandford, T.35
Schweinfurth, R.36
Shaheed, R.37
Sivakumar, S.38
Taylor, M.39
Tufts, B.40
Wallace, C.41
Wang, P.42
Weber, C.43
Bohr, M.44
more..
-
2
-
-
0842288295
-
High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering
-
V. Chan, R. Rengarajan, N. Rovedo, W. Jin, T. Hook, P. Nguyen, J. Chen, E. Nowak, X.-D. Chen, D. Lea, A. Chakravarti, V. Ku, S. Yang, A. Steegen, C. Baiocco, P. Shafer, H. Ng, S.-F. Huang, and C. Wann, "High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering" in IEDM Tech. Dig., 2003, pp. 3.8.1-3.8.4.
-
(2003)
IEDM Tech. Dig.
, pp. 1-3
-
-
Chan, V.1
Rengarajan, R.2
Rovedo, N.3
Jin, W.4
Hook, T.5
Nguyen, P.6
Chen, J.7
Nowak, E.8
Chen, X.-D.9
Lea, D.10
Chakravarti, A.11
Ku, V.12
Yang, S.13
Steegen, A.14
Baiocco, C.15
Shafer, P.16
Ng, H.17
Huang, S.-F.18
Wann, C.19
-
3
-
-
8344266076
-
Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs
-
Nov
-
"Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs" IEEE Electron Dev. Lett., vol. 25, pp. 731-733, Nov. 2004.
-
(2004)
IEEE Electron Dev. Lett.
, vol.25
, pp. 731-733
-
-
-
4
-
-
33846032325
-
Piezoresistance coefficients of (100) silicon nMOSFETs measured at low and high (similar to 1.5 GPa) channel stress
-
Jan
-
S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, "Piezoresistance coefficients of (100) silicon nMOSFETs measured at low and high (similar to 1.5 GPa) channel stress" IEEE Electron Dev. Lett., vol. 28, pp. 58-61, Jan. 2007.
-
(2007)
IEEE Electron Dev. Lett.
, vol.28
, pp. 58-61
-
-
Suthram, S.1
Ziegert, J.C.2
Nishida, T.3
Thompson, S.E.4
-
5
-
-
11144354892
-
A logic nanotechnology featuring strained-silicon
-
Apr
-
S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Y. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon" IEEE Electron Dev. Lett., vol. 25, pp. 191-193, Apr. 2004.
-
(2004)
IEEE Electron Dev. Lett.
, vol.25
, pp. 191-193
-
-
Thompson, S.E.1
Armstrong, M.2
Auth, C.3
Cea, S.4
Chau, R.5
Glass, G.6
Hoffman, T.7
Klaus, J.8
Ma, Z.Y.9
McIntyre, B.10
Murthy, A.11
Obradovic, B.12
Shifren, L.13
Sivakumar, S.14
Tyagi, S.15
Ghani, T.16
Mistry, K.17
Bohr, M.18
El-Mansy, Y.19
-
6
-
-
33646871354
-
Moore's law: The future of Si microelectronics
-
May
-
S. E. Thompson and S. Parthasarathy, "Moore's law: The future of Si microelectronics" Mater. Today, vol. 9, pp. 20-25, May 2006.
-
(2006)
Mater. Today
, vol.9
, pp. 20-25
-
-
Thompson, S.E.1
Parthasarathy, S.2
-
7
-
-
20544447617
-
Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs
-
S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, "Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs" in IEDM Tech. Dig., 2004, pp. 221-224.
-
(2004)
IEDM Tech. Dig.
, pp. 221-224
-
-
Thompson, S.E.1
Sun, G.2
Wu, K.3
Lim, J.4
Nishida, T.5
-
8
-
-
33646043420
-
Uniaxialprocess-induced strained-Si: Extending the CMOS roadmap
-
May
-
S. E. Thompson, G. Y. Sun, Y. S. Choi, and T. Nishida, "Uniaxialprocess-induced strained-Si: Extending the CMOS roadmap" IEEE Trans. Electron Dev., vol. 53, pp. 1010-1020, May 2006.
-
(2006)
IEEE Trans. Electron Dev.
, vol.53
, pp. 1010-1020
-
-
Thompson, S.E.1
Sun, G.Y.2
Choi, Y.S.3
Nishida, T.4
-
9
-
-
20544470957
-
Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain
-
Z. Wei, A. Seabaugh, V. Adams, D. Jovanovic, and B. Winstead, "Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain" IEEE Electron Dev. Lett., vol. 26, pp. 410-412, 2005.
-
(2005)
IEEE Electron Dev. Lett.
, vol.26
, pp. 410-412
-
-
Wei, Z.1
Seabaugh, A.2
Adams, V.3
Jovanovic, D.4
Winstead, B.5
-
10
-
-
31944448128
-
Strain-induced changes in the gate tunneling currents in p-channel metal-oxide-semiconductor field-effect transistors
-
Jan
-
X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, and S. E. Thompson, "Strain-induced changes in the gate tunneling currents in p-channel metal-oxide-semiconductor field-effect transistors" Appl. Phys. Lett., vol. 88, Jan. 2006.
-
(2006)
Appl. Phys. Lett.
, vol.88
-
-
Yang, X.1
Lim, J.2
Sun, G.3
Wu, K.4
Nishida, T.5
Thompson, S.E.6
-
11
-
-
21644452652
-
Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing
-
H. S. Yang, R. Malik, S. Narasimha, Y. Li, R. Divakaruni, P. Agnello, S. Allen, A. Antreasyan, J. C. Arnold, K. Bandy, M. Belyansky, A. Bonnoit, G. Bronner, V. Chan, X. Chen, Z. Chen, D. Chidambarrao, A. Chou, W. Clark, S. W. Crowder, B. Engel, H. Harifuchi, S. F. Huang, R. Jagannathan, F. F. Jamin, Y. Kohyama, H. Kuroda, C. W. Lai, H. K. Lee, W. H. Lee, E. H. Lim, W. Lai, A. Mallikarjunan, K. Matsumoto, A. McKnight, J. Nayak, H. Y. Ng, S. Panda, R. Rengarajan, M. Steigerwalt, S. Subbanna, K. Subramanian, J. Sudijono, G. Sudo, S. P. Sun, B. Tessier, Y. Toyoshima, P. Tran, R. Wise, R. Wong, I. Y. Yang, C. H. Wann, L. T. Su, M. Horstmann, T. Feudel, A. Wei, K. Frohberg, G. Burbach, M. Gerhardt, M. Lenski, R. Stephan, K. Wieczorek, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, P. Huebler, S. Luning, R. van Bentum, G. Grasshoff, C. Schwan, E. Ehrichs, S. Goad, J. Buller, S. Krishnan, D. Greenlaw, M. Raab, and N. Kepler, "Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing" in IEDM Tech. Dig., 2004, pp. 1075-1077.
-
(2004)
IEDM Tech. Dig.
, pp. 1075-1077
-
-
Yang, H.S.1
Malik, R.2
Narasimha, S.3
Li, Y.4
Divakaruni, R.5
Agnello, P.6
Allen, S.7
Antreasyan, A.8
Arnold, J.C.9
Bandy, K.10
Belyansky, M.11
Bonnoit, A.12
Bronner, G.13
Chan, V.14
Chen, X.15
Chen, Z.16
Chidambarrao, D.17
Chou, A.18
Clark, W.19
Crowder, S.W.20
Engel, B.21
Harifuchi, H.22
Huang, S.F.23
Jagannathan, R.24
Jamin, F.F.25
Kohyama, Y.26
Kuroda, H.27
Lai, C.W.28
Lee, H.K.29
Lee, W.H.30
Lim, E.H.31
Lai, W.32
Mallikarjunan, A.33
Matsumoto, K.34
McKnight, A.35
Nayak, J.36
Ng, H.Y.37
Panda, S.38
Rengarajan, R.39
Steigerwalt, M.40
Subbanna, S.41
Subramanian, K.42
Sudijono, J.43
Sudo, G.44
Sun, S.P.45
Tessier, B.46
Toyoshima, Y.47
Tran, P.48
Wise, R.49
Wong, R.50
Yang, I.Y.51
Wann, C.H.52
Su, L.T.53
Horstmann, M.54
Feudel, T.55
Wei, A.56
Frohberg, K.57
Burbach, G.58
Gerhardt, M.59
Lenski, M.60
Stephan, R.61
Wieczorek, K.62
Schaller, M.63
Salz, H.64
Hohage, J.65
Ruelke, H.66
Klais, J.67
Huebler, P.68
Luning, S.69
Van Bentum, R.70
Grasshoff, G.71
Schwan, C.72
Ehrichs, E.73
Goad, S.74
Buller, J.75
Krishnan, S.76
Greenlaw, D.77
Raab, M.78
Kepler, N.79
more..
-
13
-
-
0038721289
-
Basic mechanisms and modeling of single-event upset in digital microelectronics
-
Jun
-
[P. E. Dodd and L. W. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics" IEEE Trans. Nucl. Sci., vol. 50, pp. 583-602, Jun. 2003.
-
(2003)
IEEE Trans. Nucl. Sci.
, vol.50
, pp. 583-602
-
-
Dodd, P.E.1
Massengill, L.W.2
-
14
-
-
46149113480
-
Future of strained Si/semiconductors in nanoscale MOSFETs
-
S. E. Thompson, S. Suthram, Y. Sun, G. Sun, S. Parthasarathy, M. Chu, and T. Nishida, "Future of strained Si/semiconductors in nanoscale MOSFETs" in IEDM Tech. Dig., 2006, pp. 1-4.
-
(2006)
IEDM Tech. Dig.
, pp. 1-4
-
-
Thompson, S.E.1
Suthram, S.2
Sun, Y.3
Sun, G.4
Parthasarathy, S.5
Chu, M.6
Nishida, T.7
-
15
-
-
27744534863
-
Mobility enhancement
-
Sep.-Oct
-
N. Mohta and S. E. Thompson, "Mobility enhancement" IEEE Circuits Dev., vol. 21, pp. 18-23, Sep.-Oct. 2005.
-
(2005)
IEEE Circuits Dev.
, vol.21
, pp. 18-23
-
-
Mohta, N.1
Thompson, S.E.2
-
16
-
-
0001038893
-
Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys
-
M. V. Fischetti and S. E. Laux, "Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys" J. Appl. Phys., vol. 80, pp. 2234-2252, 1996.
-
(1996)
J. Appl. Phys.
, vol.80
, pp. 2234-2252
-
-
Fischetti, M.V.1
Laux, S.E.2
-
17
-
-
0028727361
-
Critical-evaluation of the pulsed-laser method for single event effects testing and fundamental-studies
-
Dec
-
J. S. Melinger, S. Buchner, D. McMorrow, W. J. Stapor, T. R. Weatherford, and A. B. Campbell, "Critical-evaluation of the pulsed-laser method for single event effects testing and fundamental-studies" IEEE Trans. Nucl. Sci., vol. 41, pp. 2574-2584, Dec. 1994.
-
(1994)
IEEE Trans. Nucl. Sci.
, vol.41
, pp. 2574-2584
-
-
Melinger, J.S.1
Buchner, S.2
McMorrow, D.3
Stapor, W.J.4
Weatherford, T.R.5
Campbell, A.B.6
-
18
-
-
0036956196
-
Subbandgap laser-induced single event effects: Carrier generation via two-photon absorption
-
Dec
-
D. McMorrow, W. T. Lotshaw, J. S. Melinger, S. Buchner, and R. L. Pease, "Subbandgap laser-induced single event effects: Carrier generation via two-photon absorption" IEEE Trans. Nucl. Sci., vol. 49, pp. 3002-3008, Dec. 2002.
-
(2002)
IEEE Trans. Nucl. Sci.
, vol.49
, pp. 3002-3008
-
-
McMorrow, D.1
Lotshaw, W.T.2
Melinger, J.S.3
Buchner, S.4
Pease, R.L.5
-
19
-
-
0023534153
-
Transient measurements of ultrafast charge collection in semicouductor diodes
-
R. S. Wagner, J. M. Bradley, N. Bordes, C. J. Maggiore, D. N. Sinha, and R. B. Hammond, "Transient measurements of ultrafast charge collection in semicouductor diodes" IEEE Trans. Nucl. Sci., vol. 34, pp. 1240-1245, 1987.
-
(1987)
IEEE Trans. Nucl. Sci.
, vol.34
, pp. 1240-1245
-
-
Wagner, R.S.1
Bradley, J.M.2
Bordes, N.3
Maggiore, C.J.4
Sinha, D.N.5
Hammond, R.B.6
-
20
-
-
0035388003
-
Development of a new data collection system and chamber for microbeam and laser investigations of single event phenomena
-
Jul
-
J. S. Laird, T. Hirao, H. Mori, S. Onoda, T. Kamiya, and H. Itoh, "Development of a new data collection system and chamber for microbeam and laser investigations of single event phenomena" Nucl. Instrum. Methods in Phys. Res. Section B-Beam Interactions With Mater. and Atoms, vol. 181, pp. 87-94, Jul. 2001.
-
(2001)
Nucl. Instrum. Methods in Phys. Res. Section B-Beam Interactions with Mater. and Atoms
, vol.181
, pp. 87-94
-
-
Laird, J.S.1
Hirao, T.2
Mori, H.3
Onoda, S.4
Kamiya, T.5
Itoh, H.6
-
21
-
-
72349094292
-
-
FLOODS/FLOOPS Manual Gainesville, FL, 2008 [Online]. Available: http
-
M. E. Law, FLOODS/FLOOPS Manual Gainesville, FL, 2008 [Online]. Available: http://www.flooxs.tec.ufl.edu
-
-
-
Law, M.E.1
-
22
-
-
58849131711
-
-
M.S. thesis, Elect. Eng. Dept., Vanderbilt Univ., Nashville, TN
-
O. A. Amusan, "Analysis of single event vulnerabilities in a 130 nm CMOS technology" M.S. thesis, Elect. Eng. Dept., Vanderbilt Univ., Nashville, TN, 2006.
-
(2006)
Analysis of Single Event Vulnerabilities in A 130 Nm CMOS Technology
-
-
Amusan, O.A.1
-
23
-
-
36448948305
-
A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependent idsat
-
R. Li, L. Yu, H. Xin, Y. Dong, K. Tao, and C. Wang, "A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependent idsat" Semicond. Sci. Tech., vol. 22, pp. 1292-1297, 2007.
-
(2007)
Semicond. Sci. Tech.
, vol.22
, pp. 1292-1297
-
-
Li, R.1
Yu, L.2
Xin, H.3
Dong, Y.4
Tao, K.5
Wang, C.6
-
24
-
-
0043022282
-
Optical-properties of polycrystalline nickel silicides
-
Nov
-
M. Amiotti, A. Borghesi, G. Guizzetti, and F. Nava, "Optical- properties of polycrystalline nickel silicides" Phys. Rev. B, vol. 42, pp. 8939-8946, Nov. 1990.
-
(1990)
Phys. Rev. B
, vol.42
, pp. 8939-8946
-
-
Amiotti, M.1
Borghesi, A.2
Guizzetti, G.3
Nava, F.4
-
25
-
-
36749104328
-
Mechanical stress altered electron gate tunneling current and extraction of conduction band deformation potentials for germanium
-
Nov
-
Y. S. Choi, J. S. Lim, T. Numata, T. Nishida, and S. E. Thompson, "Mechanical stress altered electron gate tunneling current and extraction of conduction band deformation potentials for germanium" J. Appl. Phys., vol. 102, pp. 104507-5, Nov. 2007.
-
(2007)
J. Appl. Phys.
, vol.102
, pp. 104507-104509
-
-
Choi, Y.S.1
Lim, J.S.2
Numata, T.3
Nishida, T.4
Thompson, S.E.5
-
26
-
-
43049102361
-
Impact of mechanical stress on direct and trap-assisted gate leakage currents in p-type silicon metal-oxide-semiconductor capacitors
-
May
-
Y. S. Choi, T. Nishida, and S. E. Thompson, "Impact of mechanical stress on direct and trap-assisted gate leakage currents in p-type silicon metal-oxide-semiconductor capacitors" Appl. Phys. Lett., vol. 92, pp.173507-3, May 2008.
-
(2008)
Appl. Phys. Lett.
, vol.92
, pp. 173507-173511
-
-
Choi, Y.S.1
Nishida, T.2
Thompson, S.E.3
-
27
-
-
33747479883
-
Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress
-
Aug
-
J. S. Lim, X. Yang, T. Nishida, and S. E. Thompson, "Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress" Appl. Phys. Lett., vol. 89, pp. 073509-3, Aug. 2006.
-
(2006)
Appl. Phys. Lett.
, vol.89
, pp. 73509-73515
-
-
Lim, J.S.1
Yang, X.2
Nishida, T.3
Thompson, S.E.4
-
28
-
-
0020298427
-
Collection of charge on junction nodes from ion tracks
-
G. C. Messenger, "Collection of charge on junction nodes from ion tracks" IEEE Trans. Nucl. Sci., vol. 29, pp. 2024-2031, 1982.
-
(1982)
IEEE Trans. Nucl. Sci.
, vol.29
, pp. 2024-2031
-
-
Messenger, G.C.1
-
29
-
-
0005835226
-
AbsorptION-coefficient of silicon - An assessment of measurements and the simulation of temperature-variation
-
Jan
-
K. Bucher, J. Bruns, and H. G. Wagemann, "AbsorptION-coefficient of silicon - An assessment of measurements and the simulation of temperature-variation" J. Appl. Phys., vol. 75, pp. 1127-1132, Jan. 1994.
-
(1994)
J. Appl. Phys.
, vol.75
, pp. 1127-1132
-
-
Bucher, K.1
Bruns, J.2
Wagemann, H.G.3
-
30
-
-
0001558496
-
Use of piezoresistive materials in the measurement of displacement, force, and torque
-
W. P. Mason and R. N. Thurston, "Use of piezoresistive materials in the measurement of displacement, force, and torque" J. Acoust. Society Amer., vol. 29, pp. 1096-1101, 1957.
-
(1957)
J. Acoust. Society Amer.
, vol.29
, pp. 1096-1101
-
-
Mason, W.P.1
Thurston, R.N.2
-
31
-
-
33846693940
-
Piezoresistance effect in germanium and silicon
-
C. S. Smith, "Piezoresistance effect in germanium and silicon" Phys. Rev., vol. 94, pp. 42-49, 1954.
-
(1954)
Phys. Rev.
, vol.94
, pp. 42-49
-
-
Smith, C.S.1
-
32
-
-
0020091827
-
Alpha-particle-induced field and enhanced collection of carriers
-
C. Hu, "Alpha-particle-induced field and enhanced collection of carriers" IEEE Electron Dev. Lett., vol. 3, pp. 31-34, 1982.
-
(1982)
IEEE Electron Dev. Lett.
, vol.3
, pp. 31-34
-
-
Hu, C.1
-
33
-
-
22944483477
-
High-injection carrier dynamics generated by MeV heavy ions impacting high-speed photodetectors
-
Jul
-
J. S. Laird, T. Hirao, S. Onoda, and H. Itoh, "High-injection carrier dynamics generated by MeV heavy ions impacting high-speed photodetectors" J. Appl. Phys., vol. 98, Jul. 2005.
-
(2005)
J. Appl. Phys.
, vol.98
-
-
Laird, J.S.1
Hirao, T.2
Onoda, S.3
Itoh, H.4
-
35
-
-
0019916789
-
A graphical representation of the piezoresistance coefficients in silicon
-
Y. Kanda, "A graphical representation of the piezoresistance coefficients in silicon" IEEE Trans. Electron Dev., vol. 29, pp. 64-70, 1982.
-
(1982)
IEEE Trans. Electron Dev.
, vol.29
, pp. 64-70
-
-
Kanda, Y.1
-
36
-
-
37249070350
-
Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS
-
S. DasGupta, A. F. Witulski, B. L. Bhuva, M. L. Alles, R. A. Reed, O. A. Amusan, J. R. Ahlbin, R. D. Schrimpf, and L. W. Massengill, "Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS" IEEE Trans. Nucl. Sci., vol. 54, pp. 2407-2412, 2007.
-
(2007)
IEEE Trans. Nucl. Sci.
, vol.54
, pp. 2407-2412
-
-
Dasgupta, S.1
Witulski, A.F.2
Bhuva, B.L.3
Alles, M.L.4
Reed, R.A.5
Amusan, O.A.6
Ahlbin, J.R.7
Schrimpf, R.D.8
Massengill, L.W.9
-
38
-
-
21644432592
-
A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low- ILD and 0.57 2 SRAM cell
-
P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S. H. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, and M. Bohr, "A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low- ILD and 0.57 2 SRAM cell" in IEDM Tech. Dig., 2004, pp. 657-660.
-
(2004)
IEDM Tech. Dig.
, pp. 657-660
-
-
Bai, P.1
Auth, C.2
Balakrishnan, S.3
Bost, M.4
Brain, R.5
Chikarmane, V.6
Heussner, R.7
Hussein, M.8
Hwang, J.9
Ingerly, D.10
James, R.11
Jeong, J.12
Kenyon, C.13
Lee, E.14
Lee, S.H.15
Lindert, N.16
Liu, M.17
Ma, Z.18
Marieb, T.19
Murthy, A.20
Nagisetty, R.21
Natarajan, S.22
Neirynck, J.23
Ott, A.24
Parker, C.25
Sebastian, J.26
Shaheed, R.27
Sivakumar, S.28
Steigerwald, J.29
Tyagi, S.30
Weber, C.31
Woolery, B.32
Yeoh, A.33
Zhang, K.34
Bohr, M.35
more..
-
39
-
-
50249185641
-
A 45 nm logic technology with high-k+Metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging
-
K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McLntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, "A 45 nm logic technology with high-k+Metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging" in IEDM Tech. Dig., 2007, pp. 247-250.
-
(2007)
IEDM Tech. Dig.
, pp. 247-250
-
-
Mistry, K.1
Allen, C.2
Auth, C.3
Beattie, B.4
Bergstrom, D.5
Bost, M.6
Brazier, M.7
Buehler, M.8
Cappellani, A.9
Chau, R.10
Choi, C.H.11
Ding, G.12
Fischer, K.13
Ghani, T.14
Grover, R.15
Han, W.16
Hanken, D.17
Hattendorf, M.18
He, J.19
Hicks, J.20
Huessner, R.21
Ingerly, D.22
Jain, P.23
James, R.24
Jong, L.25
Joshi, S.26
Kenyon, C.27
Kuhn, K.28
Lee, K.29
Liu, H.30
Maiz, J.31
McLntyre, B.32
Moon, P.33
Neirynck, J.34
Pae, S.35
Parker, C.36
Parsons, D.37
Prasad, C.38
Pipes, L.39
Prince, M.40
Ranade, P.41
Reynolds, T.42
Sandford, J.43
Shifren, L.44
Sebastian, J.45
Seiple, J.46
Simon, D.47
Sivakumar, S.48
Smith, P.49
Thomas, C.50
Troeger, T.51
Vandervoorn, P.52
Williams, S.53
Zawadzki, K.54
more..
|