Serial-link bus: A low-power on-chip bus architecture

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 541-546

  Ghoneima, Maged ^a   Ismail, Yehea ^a   Khellah, Muhammad ^b   Tschanz, James ^b   De, Vivek ^b  

^a NORTHWESTERN UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY CODES; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CONDUCTIVITY; ENERGY DISSIPATION; MULTIPLEXING;

BUS ARCHITECTURE; COUPLING CAPACITANCE; INTERCONNECT RESISTIVITY; SERIAL LINK BUS (SLB);

COMPUTER AIDED DESIGN;

EID: 33751416871     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560126     Document Type: Conference Paper

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