Online prediction of applications cache utility

Proceedings - 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007

Volumn , Issue , 2007, Pages 169-177

  Moretó, Miquel ^a,b   Cazorla, Francisco J ^c   Ramirez, Alex ^a,b,c   Valero, Mateo ^a,b,c  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b European Network of Excellence on High Performance Embedded Architecture and Compilation   (United States)

^c BARCELONA SUPERCOMPUTING CENTER   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; CACHE MEMORY; COMPUTER HARDWARE; COMPUTER SYSTEMS; EMBEDDED SYSTEMS; HARDWARE; MECHANISMS; MICROPROCESSOR CHIPS; STANDARDS;

AVERAGE ERRORS; BRANCH PREDICTORS; EMBEDDED COMPUTER SYSTEMS; EXECUTION UNITS; GENERAL PURPOSE ARCHITECTURES; HARDWARE COSTS; HARDWARE IMPLEMENTATIONS; HIGH-ACCURACY; INTERNATIONAL CONFERENCES; L2 CACHE; MAXIMUM ERROR; MODELING AND SIMULATION; MULTITHREADED ARCHITECTURES; ON-LINE PREDICTION; OPERATING SYSTEMS; POWER CONSUMPTION; RE-CONFIGURABLE; RECONFIGURABLE HARDWARE; RUN-TIME; SINGLE THREADED; STANDARD DEVIATION;

COMPUTER ARCHITECTURE;

EID: 47749129277     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSAMOS.2007.4285748     Document Type: Conference Paper

References (22)

1. M. J. Serrano, R. Wood, and M. Nemirovsky. A study on multistreamed superscalar processors. Technical Report 93-05, University of California Santa Barbara, 1993.
2. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous multithreading: maximizing on-chip parallelism. In ISCA, 1995.
3. L. Hammond, B. A. Nayfeh, and K. Olukotun. A single-chip multiprocessor. Computer, 30(9):79-85, 1997.
4. F. J. Cazorla, A. Ramirez, M. Valero, and E. Fernandez. Dynamically controlled resource allocation in SMT processors. In MICRO, 2004.
5. D. Chiou, P. Jain, S. Devadas, and L. Rudolph. Dynamic cache partitioning via columnization. In Design Automation Conference, 2000.
6. M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO, 2006.
7. G. E. Suh, L. Rudolph, and S. Devadas. Dynamic partitioning of shared cache memory. Journal of Supercomputing, 28(1):7-26, 2004.
8. A. Settle, D. Connors, E. Gibert, and A. Gonzalez. A dynamically reconfigurable cache for multithreaded processors. Journal of Embedded Computing, 1(3-4), 2005.
9. S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT, 2004.
10. R. Iris Bahar and S. Manne. Power and energy reduction via pipeline balancing. In ISCA, pages 218-229, 2001.
11. A. S. Dhodapkar and J. E. Smith. Managing multi-configuration hardware via dynamic working set analysis. In ISCA, 2002.
12. R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. In MICRO, 2000.
13. D. H. Albonesi. Selective cache ways: on-demand cache resource allocation. In MICRO, 1999.
14. S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: exploiting generational behavior to reduce cache leakage power. In ISCA, 2001.
15. R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger. Evaluation techniques for storage hierarchies. IBM Systems Journal, 9(2):78-117, 1970.
16. T. S. Karkhanis and J. E. Smith. A first-order superscalar processor model. In ISCA, 2004.
17. P. Michaud, A. Seznec, and S. Jourdan. Exploring instruction-fetch bandwidth requirement in wide-issue superscalar processors. In PACT, 1999.
18. T. Sherwood, E. Perelman, G. Hamerly, S. Sair, and B. Calder. Discovering and exploiting program phases. IEEE Micro, 2003.
19. L. Eeckhout, S. Nussbaum, J. E. Smith, and K. De Bosschere. Statistical simulation: Adding efficiency to the computer designer's toolbox. IEEE Micro, 2003.
20. E. Ypek et al. Efficiently exploring architectural design spaces via predictive modeling. In ASPLOS, 2006.
21. S. Chheda et al. Combining compiler and runtime ipc predictions to reduce energy in next generation architectures. In CF, 2004.
22. H. Kobayashi, I. Kotera, and H. Takizawa. Locality analysis to control dynamically way-adaptable caches. Comput. Archit. News, 33(3):25-32, 2005.