A networks-on-chip architecture design space exploration - The LIB

Computers and Electrical Engineering

Volumn 35, Issue 6, 2009, Pages 817-836

  Liu, Peng ^a   Xia, Bingjie ^a   Xiang, Chunchang ^a   Wang, Xiaohang ^a   Wang, Weidong ^a   Yao, Qingdong ^a  

^a ZHEJIANG UNIVERSITY   (China)

Author keywords

IP cores; Multi processor systems on chip; Networks on chip; Protocols

Indexed keywords

APPLICATION LAYERS; APPLICATION MAPPING; APPLICATION REQUIREMENTS; APPLICATION-SPECIFIC; ARCHITECTURE DESIGNS; BUILDING BLOCKES; COMMUNICATION NETWORKS; DESIGN FLOWS; HARDWARE AND SOFTWARE; INTERACTING SYSTEM; IP CORES; MODULAR BUILDINGS; MULTI-PROCESSOR SYSTEMS-ON-CHIP; MULTIPROCESSOR-SYSTEM; NETWORKS ON CHIPS; NETWORKS-ON-CHIP; NOC ARCHITECTURES; ON-CHIP INTERCONNECTION NETWORK; ON-CHIP NETWORKS; PHYSICAL LAYERS; PROGRAMMING MODELS; PROTOCOLS; SOFTWARE RADIO; SYSTEMS ON CHIPS; THREE-LAYER;

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; DESIGN; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; INTERCONNECTION NETWORKS; INTERNET PROTOCOLS; LASER DAMAGE; MICROPROCESSOR CHIPS; MODULAR CONSTRUCTION; MULTIPROCESSING SYSTEMS; PHILOSOPHICAL ASPECTS; RADIO COMMUNICATION; SOFTWARE ARCHITECTURE; SPACE RESEARCH;

NETWORK ARCHITECTURE;

EID: 70350574659     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2008.11.027     Document Type: Article

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