High performance 30 nm gate bulk CMOS for 45 nm node with Σ-shaped SiGe-SD

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 237-240

  Ohta, H ^a   Kim, Y ^a   Shimamune, Y ^a   Sakuma, T ^a   Hatada, A ^a   Katakami, A ^a   Soeda, T ^a   Kawamura, K ^a   Kokura, H ^a   Morioka, H ^a   Watanabe, T ^a   Oh, J ^a   Hayami, Y ^a   Ogura, J ^a   Tajima, M ^a   Mori, T ^a   Tamura, N ^a   Kojima, M ^a   Hashimoto, K ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

HOLE MOBILITY ENHANCEMENT; SHALLOW TRENCH ISOLATION (STI); SOURCE/DRAIN EXTENSION (SDE);

DRAIN CURRENT; ELECTRON MOBILITY; GATES (TRANSISTOR); HOLE MOBILITY; MOSFET DEVICES; SILICON NITRIDE;

CMOS INTEGRATED CIRCUITS;

EID: 33847717077     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. T.Ghani, M.Armstrong, C.Auth, M.Bost, P. Charvat et al, "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors" : IEDM Tech. Dig., pp. 978-980, 2003.
2. K.Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani et al, "Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology" : Symp. VLSI Tech., pp. 50-51, 2004.
3. P.R.Chidambaram, B.A.Smith, L.H.Hall, H.Bu, S.Chakravarthi et al, "35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37nm Gate Length PMOS" : Symp. VLSI Tech., pp. 48-49, 2004.
4. K.Goto, Y.Tagawa, H.Ohta, H.Morioka, S.Pidin, Y.Momiyama, H.Kokura, S.Inagaki, N.Tamura, M,Hori et al, "High Performance 25 nm Gate CMOSFETs for 65 nm Node High Speed MPUs" : IEDM Tech. Dig., pp. 623-626, 2003.
5. S.K.H.Fung, H.T.Huang, S.M.Cheng, K.L.Cheng, S.W.Wang et al, "65nm CMOS High Speed, General Purpose and Low Power Transistor Technology for High Volume Foundry Application" : Symp. VLSI Tech., pp. 92-93, 2004.
6. T.Ueno, H.S.Rhee, S.H.Lee, H.Lee, D.S.Shin et al, "Dramatically Enhanced Perform ance of Recessed SiGe Source-Drain PMOS by In-Situ Etch and Regrowth Technique (InSERT)", : Symp. VLSI Tech., pp. 24-25, 2005.
7. J.H.Yang, J.E.Park, J.W.Lee, K.S.Chu, J.H.Ku, et al, "Ultimate Solution for Low Thermal Budget Gate Spacer and Etch Stopper to Retard Short Channel Effect in Sub-90nm Devices" : Symp. VLSI Tech., pp. 55-56, 2003.