Impact of technology scaling on digital subthreshold circuits

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008

Volumn , Issue , 2008, Pages 179-184

  Bol, David ^a   Ambroise, Renaud ^a   Flandre, Denis ^a   Legat, Jean Didier ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CONSERVATION; DELAY CIRCUITS; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; EFFICIENCY; ENERGY POLICY; NANOTECHNOLOGY; TECHNOLOGY; THRESHOLD ELEMENTS;

CHANNEL LENGTHS; ENERGY CONSUMPTION; LOSS OF ENERGY; PROCESS VARIABILITY; ROBUSTNESS ISSUES; STATIC ENERGY; STATIC-NOISE MARGIN; SUB THRESHOLDS; SUBTHRESHOLD CIRCUITS; TECHNOLOGY SCALING; TOTAL ENERGY CONSUMPTION; ULTRA-LOW ENERGY; VLSI TECHNOLOGIES;

ENERGY EFFICIENCY;

EID: 51849132489     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2008.75     Document Type: Conference Paper

References (13)

1. A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40(1), pp. 310-319, 2005.
2. A. Raychowdhury, B. Paul, and K. Roy, "Computing with sub-threshold leakage: device/circuit/architecture co-design for ultra-low-power subthreshold operation," IEEE Trans. VLSI Systems, vol. 13(11), pp. 1213-1224, 2005.
3. S. Hanson, M. Seok, D. Sylvester, and D. Blauw, "Nanometer device scaling in subthreshold circuits," ACM/IEEE Des. Autom. Conf., pp. 700-705, 2007.
4. J. Kwong and A. P. Chandrakasa, "Variation-driven device sizing for minimum energy sub-threshold circuits," ACM/IEEE Int. Symp. Low-Power Electronics Des., pp. 8-13, 2006.
5. W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45nm early design exploration," IEEE Trans. Electron Devices, vol. 53(11), pp. 2816-2823, 2006.
6. R. Dennard, F. Gaensslen, V. Rideout, E. Bassous, and A. Leblanc, "Design of ion-implanted MOSFET's with very small physical dimensions," IEEE J. Solid-State Circuits, vol. 9(5), pp. 256-268, 1974.
7. M. Dunga et al., "BSIM4.6.1 MOSFET model," 2007.
8. Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. Ko, and Y. Cheng, "Threshold voltage model for deep-submicrometer MOSFET's," IEEE Trans. Electron Devices, vol. 40(1), pp. 86-95, 1993.
9. H. Ohta et al., "High performance 30 nm gate bulk CMOS for 45 nm node with σ-shaped SiGe-SD," IEEE Int. Electron Device Meeting, 2005.
10. Q. Huang, F. Piazza, P. Orsatti, and T. Ohguro, "The impact of scaling down to deep submicron on CMOS RF circuits," IEEE J. Solid-State Circuits, vol. 33(7), pp. 1023-1036, 1998.
11. B. Paul, A. Raychowdhury, and K. Roy, "Device optimization for digital subthreshold logic operation," IEEE Trans. Electron Devices, vol. 52(2), pp. 237-247, 2005.
12. Semiconductor Industry Association, "The international technology roadmap for semiconductors," 2005.
13. M. Seok, S. Hanson, D. Sylvester, and D. Blauw, "Analysis and optimization of sleep modes in subthreshold circuit design," ACM/IEEE Des. Autom. Conf., pp. 694-699, 2007.