Balancing resource utilization to mitigate power density in processor pipelines

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2005, Pages 294-304

  Powell, Michael D ^a   Schuchman, Ethan ^a   Vijaykumar, T N ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYMMETRIC; POWER DENSITY; REGISTER FILES; VOLTAGE SCALING;

COMPUTATIONAL COMPLEXITY; ELECTRIC POWER UTILIZATION; PROBLEM SOLVING; PROGRAM PROCESSORS; RESOURCE ALLOCATION; SCHEDULING;

PIPELINE PROCESSING SYSTEMS;

EID: 33749378574     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2005.14     Document Type: Conference Paper

References (18)

1. D. Brooks and M. Martonosi. Dynamic thermal management for high-performance microprocessors. In Seventh International Symposium on High Performance Computer Architecture (HPCA), pages 171-182, Jan. 2001.
2. D. Brooks, V. Tiwari, and M. Martonosi, Wattch: A framework for architectural-level power analysis and optimizations. In Pro-ceedings of the 27th Annual International Symposium on Computer Architecture, pages 83-94, June 2000.
3. M. D. Brown, J. Stark, and Y. N. Patt. Select-free instruction scheduling logic. In Proceedings of the 34th International Symposium on Microarchitecture (MICRO 34), pages 204-213, Dec. 2001.
4. D. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin-Madison, June 1997.
5. A. Buyuktosunoglu, A. El-Moursy, and D. H. Albonesi. An oldest-first selection logic implementation for non-compacting issue queues. In 15th International ASIC/SOC Conference, pages 31-35, Sept. 2002.
6. P. Chaparro, G. Magklis, J. Gonzalez, and A. Gonzalez. Distributing the frontend for temperature reduction, In Eleventh International Symposium on High Performance Computer Architecture (HPCA), pages 61-70, Feb, 2005.
7. J. Clabes, J. Friedrich, M. Sweet, J. DiLullo, S. Chu, D. Plass, J. Dawson, P. Muench, L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz, S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill, and S. Dodson. Design and implementation of the powcrS microprocessor. In Proceedings of the 41st Design Automation Conference (DAC), 2004.
8. J. A. Farrell and T. C. Fisher. Issue logic for a 600-mhz out-of-order execution microprocessor. IEEE Journal of Solid-State Circuits, 33(5):707-712, 1998.
9. D. Folegnani and A. Gonzalez. Energy-effective issue logic. In Proceedings of the 28th International Symposium on Computer Architecture (ISCA 28), pages 230-239, June 2001.
10. S. Gunther, F. Binns, D. M. Carmcan, and J. C. Hall. Managing the impact of increasing microprocessor power consumption. In Intel Technology Journal Q1 2001, Q1 2001.
11. S. Heo, K. Barr, and K. Asanovic. Reducing power density through activity migration. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 217-222, Aug. 2003.
12. S. Palacharla, N. P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. In Proceedings of the 24th Annual International Symposium on Computer Architecture, June 1997.
13. E. Perelman, G. Hamerly, and B. Calder. Picking statistically valid and early simulation points. In International Conference on Parallel Architectures and Compilation Techniques (PACT2003), Sept. 2003.
14. M. D. Powell, M. Gomaa, and T. N. Vijaykumar. Heat and run: Leveraging smt and cmp to manage power density through the opcrating system. In Proceedings of the Eleventh International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XI), pages 260-270, Oct. 2004.
15. K. Skadron, T. Abdelzaher, and M. R. Stan. Control-theoretic techniques and thermal-rc modeling for accurate and localized dynamic thermal management. In Eighth International Symposium on High Performance Computer Architecture (HPCA), pages IT28, Feb. 2002.
16. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware microarchitecturc. In Proceedings of the 30th International Symposium on Computer Architecture (ISCA 30), pages 2-13, June 2003.
17. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware microarchitecture: Extended discussion and results. Technical Report CS-2003-08, University of Virginia Department of Computer Science, Apr, 2003.
18. The Standard Performance Evaluation Corporation. Spec CPU2000 suite.http://www.specbench.org/osg/cpu2000/.