Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 9, 2009, Pages 1307-1320

  Zhang, Jie ^a   Patil, Nishant P ^a   Mitra, A Subhasish ^a  

^a Stanford University   (United States)

Author keywords

Carbon nanotubes (CNTs); Leakage power; Nanotechnology; Noise analysis; Probabilistic modeling

Indexed keywords

CIRCUIT PERFORMANCE; DELAY VARIATION; DESIGN PARAMETERS; DIGITAL LOGIC CIRCUIT; GROWTH TECHNIQUES; LEAKAGE POWER; METALLIC CARBON NANOTUBES; NOISE ANALYSIS; NOISE MARGINS; PROBABILISTIC ANALYSIS; PROBABILISTIC MODELING; PROBABILISTIC MODELS; QUANTITATIVE ANALYSIS; SPECIAL PROCESSING; UNDESIRABLE EFFECTS; VERY LARGE-SCALE INTEGRATION;

CARBON NANOTUBES; DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; LOGIC DESIGN; NANOTECHNOLOGY; SWITCHING CIRCUITS; VLSI CIRCUITS;

LOGIC CIRCUITS;

EID: 69649085460     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2023197     Document Type: Article

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