Design guidelines for metallic-carbon-nanotube-tolerant digital logic circuits

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 1009-1014

  Zhang, Jie ^a   Patil, Nishant P ^a   Mitra, Subhasish ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CARBON NANOTUBE FIELD EFFECT TRANSISTORS; CIRCUIT DESIGNS; CIRCUIT MODELING; CO-OPTIMIZATION; DELAY VARIATIONS; DESIGN GUIDELINES; DESIGNING ROBUST; DIGITAL LOGIC CIRCUITS; GROWTH TECHNIQUES; METALLIC CARBON NANOTUBES; NANO TUBE; NOISE MARGIN; PROCESSING TECHNIQUES; SOURCE-DRAIN;

CAPACITANCE; CARBON; DELAY CIRCUITS; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; INDUSTRIAL ENGINEERING; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; LOGIC DESIGN; METALLIC SOAPS; NANOCOMPOSITES; NANOPORES; NANOSTRUCTURED MATERIALS; NANOSTRUCTURES; NANOTECHNOLOGY; NANOTUBES; NETWORKS (CIRCUITS); OPTIMIZATION; SWITCHING CIRCUITS; SWITCHING THEORY; TESTING; TIME DELAY;

CARBON NANOTUBES;

EID: 49749114824     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484813     Document Type: Conference Paper

References (18)

1. Amlani I., et al., "First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier," Proc. IEDM, pp. 1-4 , 2006.
2. Cao Y., Clark L, "Mapping statistical process variations toward circuit performance variability: an analytical modeling approach", Proc. DAC, pp. 658-663, 2005.
3. Chen J., C. Klinke, A. Afzali and P. Avouris, "Self-aligned carbon nanotube transistors with charge transfer doping", Appl. Phys. Lett., 86, 123108, 2005.
4. Collins P., S. Arnold, P. Avouris, "Engineering carbon nanotubes and nanotube circuits using electrical breakdown", Science, vol. 292, pp. 706 - 709, 2001.
5. Deng J., H.-S. P. Wong, "A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors", Proc. SISPAD, pp. 166 - 169, 2006.
6. Deng J., et al., "Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections", Proc. ISSCC, pp. 70-588, 2007.
7. Deng J., and H. -S. P. Wong, "A Compact SPICE Model for Carbon Nanotube Field Effect Transistors Including Non-Idealities and Its Application - Part I: Model of the Intrinsic Channel Region", IEEE Trans. Elec. Dev., pp.31863194, 2007
8. Guo J., et al., "Performance Analysis and Design Optimization of Near Ballistic Carbon Nanotube Field-Effect Transistors", Proc. IEDM, pp. 703 - 706, 2004.
9. Hill, C.F., "Noise Margin and Noise Immunity in Logic Circuits", Microelectron, vol. 1, pp. 16-21, 1968.
10. http://www.itrs.net/Links/2006Update/2006Updatefinal.htm
11. Javey A., et al., "Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts and High-K Gate Dielectrics", Nano Letters, vol. 4, pp. 447-450, 2004.
12. Li Y., et al., "Preferential Growth of Semiconducting Single-Walled Carbon Nanotubes by a Plasma Enhanced CVD Method", Nano Letters, vol. 4, pp. 317-321, 2004.
13. Liu X., et al., "Detailed analysis of the mean diameter and diameter distribution of single-wall carbon nanotubes from their optical response", Phys Rev B 66, pp. 45411, 2002.
14. Nose K. and T. Sakurai, "Optimization of VDD and VTH for Low-Power and High-Speed Applications", Proc. ASPDAC, pp. 469-474, 2002.
15. Patil N., et al., "Automated Design of Misaligned-Carbon- Nanotube-Immune Circuits", Proc. DAC, pp. 958 - 961, 2007.
16. Saito R., G. Dresselhaus and M. Dresselhaus, "Physical Properties of Carbon Nanotubes", Imperial College Press, 1998.
17. Wong H.-S., et al., "Carbon Nanotube Field Effect Transistors - Fabrication, Device Physics, and Circuit Implications", Proc. ISSCC, pp. 370 - 371, 2003.
18. Zhang G., et al., "Selective Etching of Metallic Carbon Nanotubes by Gas-Phase Reaction", Science, Vol. 314, pp. 974-977, 2006.