Concurrent fault detection in random combinational logic

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 425-430

  Drineas, Petros ^a   Makris, Yiorgos ^a  

^a Yale University   (United States)

Author keywords

Built in self test; Circuit faults; Circuit testing; Costs; Degradation; Delay; Electrical fault detection; Fault detection; Hardware; Logic

Indexed keywords

BUILT-IN SELF TEST; COMPUTER HARDWARE; COSTS; DEGRADATION; ELECTRIC FAULT LOCATION; FAULT DETECTION; HARDWARE;

CIRCUIT FAULTS; CIRCUIT TESTING; DELAY; ELECTRICAL FAULT DETECTIONS; LOGIC;

LOGIC CIRCUITS;

EID: 33845304810     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194770     Document Type: Conference Paper

References (15)

1. A. Avizienis and J. P. J. Kelly, "Fault tolerance by design diversity: Concepts and experiments," IEEE Computer, vol. 17, no. 8, pp. 67-80, 1984.
2. K. K. Saluja, R. Sharma, and C. R. Kime, "A concurrent testing technique for digital circuits," IEEE TCAD, vol. 7, no. 12, pp. 1250-1260, 1988.
3. I. Voyiatzis, A. Paschalis, D. Nikolos, and C. Halatsis, "R-CBIST: An effective RAM-based input vector monitoring concurrent BIST technique," in ITC, 1998, pp. 918-925.
4. N. K. Jha and S.-J. Wang, "Design and synthesis of self-checking VLSI circuits," IEEE TCAD, vol. 12, no. 6, pp. 878-887, 1993.
5. D. Nikolos, "Optimal self-testing embedded parity checkers," IEEE TCOMP, vol. 47, no. 3, pp. 313-321, 1998.
6. N. A. Touba and E. J. McCluskey, "Logic synthesis of multilevel circuits with concurrent error detection," IEEE TCAD, vol. 16, no. 7, pp. 783-789, 1997.
7. C. Zeng, N. Saxena, and E. J. McCluskey, "Finite state machine synthesis with concurrent error detection," in ITC, 1999, pp. 672-679.
8. A. Chatterjee and R. K. Roy, "Concurrent error detection in non-linear digital circuits with applications to adaptive filters," in ICCD, 1993, pp. 606-609.
9. I. Bayraktaroglu and A. Orailoglu, "Low-cost on-line test for digital filters," in VTS, 1999, pp. 446-451.
10. Y. Makris, I. Bayraktaroglu, and A. Orailoglu, "Invariance-based on-line test for RTL controller-datapath circuits," in VTS, 2000, pp. 459-464.
11. R. Sharma and K. K. Saluja, "An implementation and analysis of a concurrent built-in self-test technique," in FTCS, 1988, pp. 164-169.
12. R. Motwani and P. Raghavan, Randomized Algorithms, Cambridge University Press, 3rd edition, 1995.
13. E. M. Sentovich et al., "SIS: a system for sequential circuit synthesis," ERL MEMO. No. UCB/ERL M92/41, EECS UC Berkeley CA 94720, 1992.
14. "ATALANTA combinational test generation tool," Available from http://www.ee.vt.edu/ha/cadtools.
15. H. K. Lee and D. S. Ha, "HOPE: An efficient parallel fault simulator for synchronous sequential circuits," IEEE TCAD, vol. 15, no. 9, pp. 1048-1058, 1996.