Synthesis of low power CED circuits based on parity codes

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 315-320

  Ghosh, Shalini ^a   Basu, Sugato ^b   Touba, Nur A ^a  

^a The University of Texas at Austin   (United States)

^b University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; AUTOMATED DESIGN PROCEDURES; CODE SELECTION; CONCURRENT ERROR DETECTION; LOGIC OPTIMIZATION; LOW POWER IMPLEMENTATION; PARITY CHECK CODES; PARTITIONING ALGORITHMS;

CONSTRAINED OPTIMIZATION; SIGNAL ENCODING; STRUCTURAL OPTIMIZATION; VLSI CIRCUITS;

LOW POWER ELECTRONICS;

EID: 33846112787     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.80     Document Type: Conference Paper

References (12)

1. Almukhaizim, S., P. Drineas, and Y. Makris, "Cost-Driven Selection of Parity Trees", Proc. of the IEEE VLSI Test Symposium (VTS), pp. 319-324, 2004.
2. Bolchini, C., F. Salice, and D. Sciuto, "A novel methodology for designing TSC networks based on the parity bit code", Proc. of the European Design and Test Conference (ED&TC-97), pp. 440-444, 1997.
3. De, K., C. Natarajan, D. Nair, and P. Banerjee, "RSYN: A system for automated synthesis of reliable multilevel circuits," IEEE Trans. on VLSI Systems, vol. 2, pp. 186-195, June 1994.
4. Goessel, M., and S. Graf, Error Detection Circuits, London, NY: McGraw-Hill, 1993.
5. Hochbaum, D., and D. Shmoys, "A best possible heuristic for the k-center problem", Mathematics of Operations Research, Vol. 10, No. 2, pp. 180-184, 1985.
6. Mohanram, K., and N. A. Touba, "Input Ordering in Concurrent Checkers to Reduce Power Consumption", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 87-95, 2002.
7. Mohanram, K., and N. A. Touba, "Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 433-440, 2003.
8. Saposhnikov, Vl. V., A. Dmitriev, M. Goessel, V. V. Saposhnikov, "Self-dual parity checking-a new method for on-line testing", Proc. of the IEEE VLSI Test Symposium (VTS), pp. 162-168, 1996.
9. Sentovich, E. M., et al., SIS: A System for Sequential Circuit Synthesis," TRM No. UCB/ERL M92/41, University of California, Berkeley, 1992.
10. Shivakumar, P., M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, "Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic", Proc. of the International Conference on Dependable Systems and Networks, pp. 389-398, 2002.
11. Sogomonjan, E. S., and M. Goessel, "Design of self-parity combinational circuits for self-testing and online detection", Proc. of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 239-246, 1993.
12. Touba, N. A., and E. J. McCluskey, "Logic Synthesis of Multilevel Circuits with Concurrent Error Detection", IEEE Trans. on Computer-Aided Design, Vol. 16, No. 7, pp. 783-789, 1997