Balanced redundancy utilization in embedded memory cores for dependable systems

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 419-427

  Choi, M ^a   Park, N ^a   Lombardi, F ^b   Kim, Y B ^b   Piuri, V ^c  

^a OKLAHOMA STATE UNIVERSITY   (United States)

^b NORTHEASTERN UNIVERSITY   (United States)

^c UNIVERSITY OF MILAN   (Italy)

Author keywords

Circuit faults; Fault tolerance; Logic; Manufacturing automation; Multichip modules; Printed circuits; Pulp manufacturing; Redundancy; System on a chip; Test equipment

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; DEFECTS; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; EQUIPMENT TESTING; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING; LEGACY SYSTEMS; LOGIC CIRCUITS; LOGIC DEVICES; MANUFACTURE; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; MULTICHIP MODULES; PRINTED CIRCUIT BOARDS; PRINTED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; REPAIR; SWITCHING SYSTEMS; SYSTEM-ON-CHIP; VLSI CIRCUITS;

CIRCUIT FAULTS; LOGIC; MANUFACTURING AUTOMATION; PULP MANUFACTURING; SYSTEM ON A CHIP; TEST EQUIPMENTS;

REDUNDANCY;

EID: 67249133133     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173540     Document Type: Conference Paper

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